Searched refs:assert (Results 251 - 275 of 647) sorted by relevance
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/gem5/src/cpu/testers/rubytest/ |
H A D | Check.cc | 170 assert(m_status == TesterStatus_Idle); 230 assert(m_status == TesterStatus_Ready); 285 // assert(getAddress() == address); 287 assert(makeLineAddress(m_address) == makeLineAddress(address)); 288 assert(data != NULL); 346 assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready); 356 assert(m_status == TesterStatus_Idle); 364 assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready);
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/gem5/src/gpu-compute/ |
H A D | shader.cc | 70 assert(i == cuList[i]->cu_id); 97 assert(mem_state->getStackBase() - mem_state->getMaxStackSize() > 112 assert(cpuPointer); 114 assert(gpuTc); 126 assert(cpuPointer); 128 assert(gpuTc); 249 assert(split_addr <= tmp_addr || split_addr - tmp_addr < block_size);
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H A D | gpu_tlb.cc | 70 assert(assoc <= size); 131 assert(translationReturnEvent.empty()); 188 assert(!set); 615 assert(!(IOPort & ~0xFFFF)); 661 assert(seg != SEGMENT_REG_MS); 669 assert(m5Reg.mode == LongMode); 918 assert(translation); 1035 assert(pkt); 1036 assert(pkt->senderState); 1069 assert(entr [all...] |
/gem5/src/dev/arm/ |
H A D | gic_v2.hh | 232 assert(ix < INT_BITS_MAX); 246 assert(ix < INT_BITS_MAX); 260 assert(ix < INT_BITS_MAX); 278 assert(ix < INT_LINES_MAX); 290 assert(ix < INT_LINES_MAX); 302 assert(ctx < sys->numRunningContexts()); 303 assert(ix < INT_LINES_MAX);
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/gem5/src/base/ |
H A D | circular_queue.hh | 307 assert(decrementable()); 320 assert(_cq); 328 assert(_cq); 391 assert(_cq && that._cq == _cq); 530 assert(hIt <= end()); 538 assert (!_empty); 641 assert(isValidIdx(idx) || moduloAdd(_tail, 1) == idx);
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/gem5/src/mem/cache/tags/ |
H A D | fa_lru.cc | 128 assert(num_erased == 1); 184 assert(blk->tag == tag); 185 assert(blk->isSecure() == is_secure); 194 assert(set == 0); 217 assert(falruBlk->inCachesMask == 0); 240 assert(blk->next == nullptr); 267 assert(blk->prev == nullptr);
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/gem5/src/cpu/o3/ |
H A D | cpu.cc | 212 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 213 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 214 assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs); 215 assert(params->numPhysVecPredRegs >= numThreads * TheISA::NumVecPredRegs); 216 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); 224 assert(RenameMode<TheISA::ISA>::equalsInit(isa[tid], isa[0])); 314 assert(this->numThreads == 1); 353 assert(o3_tc->cpu); 534 assert(!switchedOut()); 535 assert(drainStat [all...] |
H A D | lsq_impl.hh | 78 assert(numThreads > 0 && numThreads <= Impl::MaxThreads); 93 assert(params->smtLSQThreshold > params->LQEntries); 94 assert(params->smtLSQThreshold > params->SQEntries); 135 assert(activeThreads != 0); 142 assert(isDrained()); 222 assert(cachePortAvailable(is_load)); 709 assert(!isAtomic || (isAtomic && !needs_burst)); 713 assert(req); 722 assert(req); 791 assert(_re [all...] |
H A D | inst_queue_impl.hh | 98 assert(fuPool); 475 assert(dependGraph.empty()); 476 assert(instsToExecute.empty()); 590 assert(new_inst); 595 assert(freeEntries != 0); 621 assert(freeEntries == (numEntries - countInsts())); 638 assert(new_inst); 646 assert(freeEntries != 0); 668 assert(freeEntries == (numEntries - countInsts())); 684 assert(!instsToExecut [all...] |
H A D | fu_pool.cc | 180 assert(fu_idx < numFU); 190 assert(unitBusy[fu_idx]); 201 assert(unitBusy[fu_idx]);
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/gem5/src/cpu/minor/ |
H A D | lsq.cc | 91 assert(inst->translationFault == fault); 343 assert(request_ == fragmentRequests[expected_fragment_index]); 380 assert(!translationEvent.scheduled()); 445 assert(addrBlockOffset(middle_fragments_total_size, line_width) == 0); 458 assert(((middle_fragment_count * line_width) + 528 assert(numFragments >= num_disabled_fragments); 535 assert(numTranslatedFragments > 0); 565 assert(fragment->hasPaddr()); 610 assert(numIssuedFragments < numTranslatedFragments); 618 assert(numIssuedFragment [all...] |
/gem5/src/arch/hsail/ |
H A D | operand.hh | 158 assert(sizeof(OperandType) <= sizeof(uint32_t)); 159 assert(regIdx < w->maxSpVgprs); 207 assert(sizeof(OperandType) == sizeof(uint32_t)); 208 assert(regIdx < w->maxSpVgprs); 220 assert(regIdx < w->maxSpVgprs); 263 assert(sizeof(OperandType) <= sizeof(uint64_t)); 265 assert(regIdx < w->maxDpVgprs); 279 assert(sizeof(OperandType) <= sizeof(uint64_t)); 281 assert(regIdx < w->maxDpVgprs); 327 assert(regId [all...] |
/gem5/src/arch/x86/ |
H A D | pagetable_walker.cc | 79 assert(newState->isTiming()); 183 assert(state == Ready); 231 assert(!started); 244 assert(fault == NoFault || read == NULL); 260 assert(!started); 270 assert(fault == NoFault || read == NULL); 283 assert(state != Ready && state != Waiting); 602 assert(pkt->isResponse()); 603 assert(inflight); 604 assert(stat [all...] |
/gem5/src/arch/arm/ |
H A D | intregs.hh | 331 assert(index < NUM_ARCH_INTREGS); 349 assert(index < NUM_ARCH_INTREGS); 367 assert(index < NUM_ARCH_INTREGS); 385 assert(index < NUM_ARCH_INTREGS); 403 assert(index < NUM_ARCH_INTREGS); 421 assert(index < NUM_ARCH_INTREGS); 439 assert(index < NUM_ARCH_INTREGS); 457 assert(index < NUM_ARCH_INTREGS); 466 assert(reg < NUM_ARCH_INTREGS);
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/gem5/src/dev/alpha/ |
H A D | tsunami_cchip.cc | 82 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 196 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 201 assert(pkt->getSize() == sizeof(uint64_t)); 382 assert(numcpus <= Tsunami::Max_CPUs); 408 assert(numcpus <= Tsunami::Max_CPUs); 428 assert(numcpus <= Tsunami::Max_CPUs); 455 assert(size <= Tsunami::Max_CPUs); 473 assert(size <= Tsunami::Max_CPUs); 491 assert(size <= Tsunami::Max_CPUs);
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/gem5/ext/systemc/src/sysc/kernel/ |
H A D | sc_reset.cpp | 188 assert( iface_p != 0 ); 252 assert( process_p ); 278 assert( process_p ); 304 assert( process_p ); 349 assert( process_p );
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/gem5/src/cpu/testers/memtest/ |
H A D | memtest.cc | 138 assert(req->getSize() == 1); 142 assert(remove_addr != outstandingAddrs.end()); 179 assert(pkt->isWrite()); 221 assert(!retryPkt); 330 assert(retryPkt);
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/gem5/src/mem/cache/ |
H A D | cache_blk.hh | 258 assert(!isValid()); 289 assert(tick >= tickInserted); 313 assert(pkt->isLLSC()); 396 assert(pkt->isWrite()); 476 assert(status == 0);
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H A D | mshr.hh | 344 assert(inService); return pendingModified; 348 assert(inService); return postInvalidate; 352 assert(inService); return postDowngrade; 476 assert(hasTargets()); 517 assert(readyTime <= curTick());
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/gem5/src/mem/ |
H A D | noncoherent_xbar.cc | 108 assert(!pkt->isExpressSnoop()); 165 assert(routeTo.find(pkt->req) == routeTo.end()); 187 assert(route_lookup != routeTo.end()); 189 assert(slave_port_id != InvalidPortID); 190 assert(slave_port_id < respLayers.size());
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/gem5/src/dev/net/ |
H A D | i8254xGBe_defs.hh | 245 inline Addr getBuf(TxDesc *d) { assert(isLegacy(d) || isData(d)); return d->d1; } 250 inline bool vle(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 30,30); } 252 inline bool ic(TxDesc *d) { assert(isLegacy(d) || isData(d)); return isLegacy(d) && bits(d->d2, 26,26); } 261 inline bool ifcs(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 25,25); } 262 inline bool eop(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 24,24); } 263 inline bool ip(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 25,25); } 264 inline bool tcp(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 24,24); } 266 inline uint8_t getCso(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 23,16); } 267 inline uint8_t getCss(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 47,40); } 272 inline int tucse(TxDesc *d) { assert(isContex [all...] |
/gem5/ext/mcpat/ |
H A D | bus_interconnect.cc | 161 assert(bus_params.chip_coverage <= 1); 162 assert(bus_params.route_over_perc <= 1); 163 assert(link_len > 0);
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/gem5/src/arch/hsail/insts/ |
H A D | mem_impl.hh | 132 assert(se); 155 assert(ret < w->privBase + 180 assert(num_dest_operands == 1); 256 assert(!((sizeof(MemCType) - 1) & m->addr[lane])); 272 assert(num_dest_operands == 1); 281 assert(m->addr[lane] < w->spillSizePerItem); 310 assert(m->addr[lane] + sizeof(MemCType) <= w->roSize); 326 assert(m->addr[lane] < w->privSizePerItem); 433 assert(!((sizeof(CType)-1) & m->addr[lane])); 449 assert(num_src_operand [all...] |
/gem5/ext/sst/ |
H A D | ExtMaster.cc | 85 assert(nic); 167 assert(cmdI == GetS); 170 assert(cmdI == GetX);
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/gem5/src/dev/i2c/ |
H A D | bus.cc | 73 assert(pkt->getAddr() == pioAddr + SB_CONTROLS); 92 assert(pkt->getAddr() == pioAddr + SB_CONTROLS || 129 assert(devices.find(i2cAddr) != devices.end());
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