Searched refs:address (Results 26 - 50 of 119) sorted by relevance

12345

/gem5/src/systemc/tests/systemc/misc/user_guide/chpt12.1/
H A Daccessor.cpp56 address.write(addr);
58 cout << "Accessor: Data Written = " << hex << datao << " at address "
71 address.write(addr);
75 cout << "Accessor: Data Read = " << hex << datai << " from address "
H A Daccessor.h52 signal_bool_vector10& address; //output local
64 write_enable(WRITE_ENABLE), address(ADDRESS), dataout(DATAOUT)
/gem5/src/systemc/tests/systemc/misc/user_guide/chpt12.2/
H A Daccessor.cpp56 address.write(addr);
58 cout << "Accessor: Data Written = " << hex << datao << " at address "
71 address.write(addr);
75 cout << "Accessor: Data Read = " << hex << datai << " from address "
H A Daccessor.h52 signal_bool_vector10& address; //output local
68 write_enable(WRITE_ENABLE), address(ADDRESS), dataout(DATAOUT),
/gem5/src/mem/ruby/structures/
H A DPrefetcher.cc139 Prefetcher::observeMiss(Addr address, const RubyRequestType& type) argument
141 DPRINTF(RubyPrefetcher, "Observed miss for %#x\n", address);
142 Addr line_addr = makeLineAddress(address);
169 // check to see if this address is in the unit stride filter
193 // check to see if this address is in the non-unit stride filter
195 hit = accessNonunitFilter(address, &stride, alloc);
207 Prefetcher::observePfMiss(Addr address) argument
210 DPRINTF(RubyPrefetcher, "Observed partial hit for %#x\n", address);
211 issueNextPrefetch(address, NULL);
215 Prefetcher::observePfHit(Addr address) argument
223 issueNextPrefetch(Addr address, PrefetchEntry *stream) argument
288 initializeStream(Addr address, int stride, uint32_t index, const RubyRequestType& type) argument
329 getPrefetchEntry(Addr address, uint32_t &index) argument
347 accessUnitFilter(std::vector<Addr>& filter_table, uint32_t *filter_hit, uint32_t &index, Addr address, int stride, bool &alloc) argument
380 accessNonunitFilter(Addr address, int *stride, bool &alloc) argument
[all...]
H A DTimerTable.hh60 bool isSet(Addr address) const { return !!m_map.count(address); }
61 void set(Addr address, Tick ready_time);
62 void unset(Addr address);
74 // use a std::map for the address map as this container is sorted
/gem5/src/cpu/testers/directedtest/
H A DDirectedGenerator.hh46 virtual void performCallback(uint32_t proc, Addr address) = 0;
H A DSeriesRequestGenerator.hh52 void performCallback(uint32_t proc, Addr address);
H A DInvalidateGenerator.hh52 void performCallback(uint32_t proc, Addr address);
/gem5/src/systemc/tests/include/
H A DExplicitLTTarget.h55 sc_dt::uint64 address = trans.get_address(); local
56 assert(address < 400);
61 << std::hex << (unsigned int)address << ", D = 0x" << data
65 *reinterpret_cast<unsigned int*>(&mMem[address]) = data;
75 *reinterpret_cast<unsigned int*>(&mMem[address]);
79 << std::hex << (unsigned int)address
83 data = *reinterpret_cast<unsigned int*>(&mMem[address]);
H A DExplicitATTarget.h59 sc_dt::uint64 address = trans.get_address(); local
60 assert(address < 400);
69 << std::hex << (unsigned int)address << ", D = 0x" << data
73 *reinterpret_cast<unsigned int*>(&mMem[address]) = data;
85 << std::hex << (unsigned int)address
89 data = *reinterpret_cast<unsigned int*>(&mMem[address]);
124 sc_dt::uint64 address = mCurrentTransaction->get_address();
125 assert(address < 400);
127 *reinterpret_cast<unsigned int*>(&mMem[address]);
H A DSimpleATTarget1.h79 sc_dt::uint64 address = trans.get_address(); local
80 assert(address < 400);
85 << std::hex << (unsigned int)address << ", D = 0x"
89 *reinterpret_cast<unsigned int*>(&mMem[address]) = data;
93 << std::hex << (unsigned int)address << std::dec
96 data = *reinterpret_cast<unsigned int*>(&mMem[address]);
163 sc_dt::uint64 address = trans->get_address();
164 assert(address < 400);
166 *reinterpret_cast<unsigned int*>(&mMem[address]);
H A DSimpleATTarget2.h77 sc_dt::uint64 address = trans.get_address(); local
78 assert(address < 400);
83 << std::hex << (unsigned int)address << ", D = 0x" << data
87 *reinterpret_cast<unsigned int*>(&mMem[address]) = data;
91 << std::hex << (unsigned int)address
95 data = *reinterpret_cast<unsigned int*>(&mMem[address]);
139 sc_dt::uint64 address = trans->get_address();
140 assert(address < 400);
142 *reinterpret_cast<unsigned int*>(&mMem[address]);
H A DSimpleLTTarget1.h70 sc_dt::uint64 address = trans.get_address(); local
71 assert(address < 400);
76 << std::hex << (unsigned int)address
80 *reinterpret_cast<unsigned int*>(&mMem[address]) = data;
85 << std::hex << (unsigned int)address << std::dec
88 data = *reinterpret_cast<unsigned int*>(&mMem[address]);
125 sc_dt::uint64 address = trans.get_address();
127 if (address < 400) {
H A DSimpleBusLT.h60 // - address[31-28]: portId
61 // - address[27-0]: masked address
64 unsigned int getPortId(const sc_dt::uint64& address) argument
66 return (unsigned int)address >> 28;
79 unsigned int decode(const sc_dt::uint64& address) argument
81 // decode address:
84 return getPortId(address);
143 sc_dt::uint64 address = trans.get_address(); local
145 unsigned int portId = decode(address);
[all...]
/gem5/src/mem/cache/prefetch/
H A Dirregular_stream_buffer.cc76 // the entry lastAddress (named as correlated_addr_A) and the address of
104 if (mapping_B.address == (mapping_A.address + 1)) {
108 // Counter would hit 0, reassign address while keeping
110 mapping_B.address = mapping_A.address + 1;
111 addStructuralToPhysicalEntry(mapping_B.address, is_secure,
119 // if A is not valid, generate a new structural address
121 mapping_A.address = structuralAddressCounter;
123 addStructuralToPhysicalEntry(mapping_A.address,
[all...]
H A Dindirect_memory.hh70 /** Accessed address */
71 Addr address; member in struct:IndirectMemoryPrefetcher::PrefetchTableEntry
72 /** Whether this address is in the secure region */
98 : TaggedEntry(), address(0), secure(false), streamCounter(0),
105 address = 0;
168 * Update an IPD entry with a detected miss address, when the first index
170 * @param miss_addr The address that caused the miss
175 * Update an IPD entry with a detected miss address, when the second index
177 * @param miss_addr The address that caused the miss
184 * @param addr address o
[all...]
/gem5/src/dev/arm/
H A Dflash_device.hh84 /** Every logical address maps to a physical block and a physical page*/
99 /** Histogram of address accesses*/
115 void readMemory(uint64_t address, uint32_t amount,
118 accessDevice(address, amount, event, ActionRead);
121 void writeMemory(uint64_t address, uint32_t amount,
124 accessDevice(address, amount, event, ActionWrite);
131 void accessDevice(uint64_t address, uint32_t amount, Callback *event,
141 Tick accessTimes(uint64_t address, Actions accesstype);
184 /** address to logic place has a block and a page field*/
/gem5/src/cpu/testers/rubytest/
H A DCheckTable.hh49 Check* getCheck(Addr address);
51 // bool isPresent(const Address& address) const;
52 // void removeCheckFromTable(const Address& address);
59 void addCheck(Addr address);
H A DCheck.hh48 Check(Addr address, Addr pc, int _num_writers,
54 void changeAddress(Addr address);
/gem5/src/mem/
H A Dfs_translating_port_proxy.hh67 * A TranslatingPortProxy in FS mode translates a virtual address to a
68 * physical address and then calls the read/write functions of the
69 * port. If a thread context is provided the address can alway be
71 * address masking operation (such as alpha super page accesses).
100 bool tryMemsetBlob(Addr address, uint8_t v, int size) const override;
/gem5/src/base/loader/
H A Dsymtab.hh56 // find first key *larger* than desired address
72 bool insert(Addr address, std::string symbol);
84 findSymbol(Addr address, std::string &symbol) const argument
86 ATable::const_iterator i = addrTable.find(address);
91 // address. For simplicity, just return the first one.
97 findAddress(const std::string &symbol, Addr &address) const
103 address = (*i).second;
108 /// address (e.g., the label for the enclosing function).
109 /// @param addr The address to look up.
111 /// @param symaddr Return reference for symbol address
[all...]
/gem5/src/gpu-compute/
H A Dshader.hh171 void AccessMem(uint64_t address, void *ptr, uint32_t size, int cu_id,
174 void ReadMem(uint64_t address, void *ptr, uint32_t sz, int cu_id);
176 void ReadMem(uint64_t address, void *ptr, uint32_t sz, int cu_id,
179 void WriteMem(uint64_t address, void *ptr, uint32_t sz, int cu_id);
181 void WriteMem(uint64_t address, void *ptr, uint32_t sz, int cu_id,
/gem5/src/mem/ruby/system/
H A DGPUCoalescer.cc412 GPUCoalescer::handleLlsc(Addr address, GPUCoalescerRequest* request) argument
421 if (!m_dataCache_ptr->isLocked(address, m_version)) {
438 m_dataCache_ptr->clearLocked(address);
444 m_dataCache_ptr->setLocked(address, m_version);
445 } else if ((m_dataCache_ptr->isTagPresent(address)) &&
446 (m_dataCache_ptr->isLocked(address, m_version))) {
448 // Normal writes should clear the locked address
450 m_dataCache_ptr->clearLocked(address);
456 GPUCoalescer::writeCallback(Addr address, DataBlock& data) argument
458 writeCallback(address, MachineType_NUL
462 writeCallback(Addr address, MachineType mach, DataBlock& data) argument
470 writeCallback(Addr address, MachineType mach, DataBlock& data, Cycles initialRequestTime, Cycles forwardRequestTime, Cycles firstResponseTime) argument
483 writeCallback(Addr address, MachineType mach, DataBlock& data, Cycles initialRequestTime, Cycles forwardRequestTime, Cycles firstResponseTime, bool isRegion) argument
538 readCallback(Addr address, DataBlock& data) argument
544 readCallback(Addr address, MachineType mach, DataBlock& data) argument
552 readCallback(Addr address, MachineType mach, DataBlock& data, Cycles initialRequestTime, Cycles forwardRequestTime, Cycles firstResponseTime) argument
566 readCallback(Addr address, MachineType mach, DataBlock& data, Cycles initialRequestTime, Cycles forwardRequestTime, Cycles firstResponseTime, bool isRegion) argument
1036 evictionCallback(Addr address) argument
1052 atomicCallback(Addr address, MachineType mach, const DataBlock& data) argument
1171 mapAddrToPkt(Addr address) argument
[all...]
/gem5/src/systemc/tests/tlm/endian_conv/
H A Dtestall.py50 - base address (0..1023) at bus_width steps
51 - offset address (0..bus width) with a higher priority for 0
52 - address in initiator buffer uniform random
75 """ contains read_not_write, address, length, byte_enable,
82 (self.address, self.length, self.bus_width, self.data_width, \
115 address = addr_base + addr_offset,
172 curr_address = txn.address
185 address = curr_address,
191 if curr_address == reset_address: curr_address = txn.address
209 address
[all...]

Completed in 26 milliseconds

12345