Searched refs:SimObject (Results 51 - 75 of 357) sorted by relevance
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| /gem5/src/mem/ruby/network/simple/ |
| H A D | SimpleLink.py | 32 from m5.SimObject import SimObject
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| /gem5/src/sim/power/ |
| H A D | MathExprPowerModel.py | 38 from m5.SimObject import SimObject
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| H A D | thermal_node.cc | 49 : SimObject(p), id(-1), isref(false), temp(0.0f)
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| /gem5/src/dev/arm/ |
| H A D | display.cc | 45 : SimObject(p)
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| /gem5/src/sim/ |
| H A D | DVFSHandler.py | 40 from m5.SimObject import SimObject
47 class DVFSHandler(SimObject):
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| H A D | ClockDomain.py | 41 from m5.SimObject import SimObject
45 class ClockDomain(SimObject):
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| H A D | ClockedObject.py | 38 from m5.SimObject import SimObject
60 class ClockedObject(SimObject):
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| H A D | Root.py | 31 from m5.SimObject import SimObject
35 class Root(SimObject):
46 # If SimObject ever implements __new__, we may want to pass
50 Root._the_instance = SimObject.__new__(cls)
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| /gem5/src/arch/mips/ |
| H A D | MipsISA.py | 38 from m5.SimObject import SimObject
42 class MipsISA(SimObject):
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| /gem5/src/mem/ruby/structures/ |
| H A D | ReplacementPolicy.py | 32 from m5.SimObject import SimObject
34 class ReplacementPolicy(SimObject):
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| /gem5/util/systemc/systemc_within_gem5/systemc_simple_object/ |
| H A D | SystemC_Example.py | 29 from m5.SimObject import SimObject
44 # This is a standard gem5 SimObject class with no special accomodation for the
46 class Gem5_Feeder(SimObject):
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| /gem5/src/base/vnc/ |
| H A D | Vnc.py | 38 from m5.SimObject import SimObject
43 class VncInput(SimObject):
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| /gem5/src/cpu/o3/ |
| H A D | FUPool.py | 41 from m5.SimObject import SimObject
46 class FUPool(SimObject):
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| /gem5/src/dev/ |
| H A D | Platform.py | 29 from m5.SimObject import SimObject
33 class Platform(SimObject):
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| /gem5/src/dev/i2c/ |
| H A D | I2C.py | 38 from m5.SimObject import SimObject
42 class I2CDevice(SimObject):
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| /gem5/src/mem/ |
| H A D | AddrMapper.py | 39 from m5.SimObject import SimObject
47 class AddrMapper(SimObject):
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| H A D | ExternalMaster.py | 42 from m5.SimObject import SimObject
44 class ExternalMaster(SimObject):
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| H A D | ExternalSlave.py | 39 from m5.SimObject import SimObject
41 class ExternalSlave(SimObject):
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| /gem5/src/mem/cache/compressors/ |
| H A D | Compressors.py | 31 from m5.SimObject import SimObject
33 class BaseCacheCompressor(SimObject):
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| /gem5/src/systemc/core/ |
| H A D | SystemC.py | 28 from m5.SimObject import SimObject, cxxMethod
31 # simulation. It receives gem5 SimObject lifecycle callbacks (init, regStats,
33 class SystemC_Kernel(SimObject):
39 # inherits from SimObject in python, but the c++ version, sc_core::sc_object,
40 # doesn't inherit from gem5's c++ SimObject class.
41 class SystemC_ScObject(SimObject):
48 # sc_core::sc_object inherits from SimObject, even though SystemC_ScObject
52 # Hide the cxx_exports from SimObject since we don't inherit from
53 # SimObject o
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| /gem5/src/dev/storage/ |
| H A D | DiskImage.py | 29 from m5.SimObject import SimObject
31 class DiskImage(SimObject):
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| /gem5/src/dev/ps2/ |
| H A D | PS2.py | 38 from m5.SimObject import SimObject
42 class PS2Device(SimObject):
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| /gem5/src/mem/cache/tags/indexing_policies/ |
| H A D | IndexingPolicies.py | 31 from m5.SimObject import SimObject
33 class BaseIndexingPolicy(SimObject):
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| /gem5/src/mem/ruby/network/ |
| H A D | MessageBuffer.py | 31 from m5.SimObject import SimObject
33 class MessageBuffer(SimObject):
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| /gem5/src/arch/x86/bios/ |
| H A D | e820.hh | 54 class E820Entry : public SimObject
64 SimObject(p), addr(p->addr), size(p->size), type(p->range_type)
68 class E820Table : public SimObject
75 E820Table(Params *p) : SimObject(p), entries(p->entries)
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