Searched refs:SimObject (Results 276 - 300 of 357) sorted by relevance

<<1112131415

/gem5/src/mem/ruby/structures/
H A D	Prefetcher.hh	81 class Prefetcher : public SimObject
/gem5/src/sim/
H A D	clock_domain.cc	61 SimObject::regStats();
H A D	serialize.hh	67 class SimObject; 90 SimObject *&value); 128 * True SimObjects (deriving from SimObject), and 2) child objects 132 * automatically by the SimObject base class (see 133 * SimObject::serializeAll(). 637 objParamIn(CheckpointIn &cp, const std::string &name, SimObject * &param); 685 SimObject *sptr; \
H A D	dvfs_handler.cc	62 : SimObject(p),
/gem5/src/cpu/kvm/
H A D	vm.hh	291 class KvmVM : public SimObject 458 * SimObject::startup() path. Since the call order of 459 * SimObject::startup() is not guaranteed, we simply defer some
/gem5/src/cpu/testers/traffic_gen/
H A D	dram_gen.cc	52 DramGen::DramGen(SimObject &obj,
/gem5/src/arch/arm/
H A D	stage2_mmu.cc	52 : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb),
H A D	ArmSystem.py	41 from m5.SimObject import *
H A D	interrupts.hh	59 class Interrupts : public SimObject 83 Interrupts(Params * p) : SimObject(p), cpu(NULL)
/gem5/src/dev/arm/
H A D	base_gic.cc	81 : SimObject(p)
/gem5/src/dev/net/
H A D	dist_etherlink.hh	64 class DistEtherLink : public SimObject
H A D	etherswitch.hh	51 class EtherSwitch : public SimObject
H A D	etherlink.cc	70 : SimObject(p) 98 return SimObject::getPort(if_name, idx);
/gem5/src/mem/cache/prefetch/
H A D	delta_correlating_prediction_tables.cc	39 DeltaCorrelatingPredictionTablesParams *p) : SimObject(p),
H A D	base.hh	373 * Add a SimObject and a probe name to listen events from 374 * @param obj The SimObject pointer to listen from 377 void addEventProbe(SimObject *obj, const char *name);
/gem5/src/systemc/core/
H A D	kernel.cc	60 SimObject(params), t0Event(this, false, EventBase::Default_Pri - 1)
/gem5/src/mem/
H A D	addr_mapper.hh	57 class AddrMapper : public SimObject
H A D	mem_checker_monitor.hh	54 class MemCheckerMonitor : public SimObject
H A D	mem_checker.hh	72 class MemChecker : public SimObject 376 : SimObject(p),
H A D	mem_checker_monitor.cc	52 : SimObject(params), 84 return SimObject::getPort(if_name, idx);
/gem5/src/cpu/pred/
H A D	loop_predictor.hh	46 class LoopPredictor : public SimObject
/gem5/src/python/m5/
H A D	main.py	304 from . import SimObject 307 objects = list(SimObject.allClasses.keys()) 310 obj = SimObject.allClasses[name]
/gem5/src/cpu/o3/
H A D	fu_pool.cc	85 : SimObject(p)
/gem5/src/dev/storage/
H A D	ide_disk.hh	207 class IdeDisk : public SimObject
/gem5/src/mem/ruby/network/fault_model/
H A D	FaultModel.cc	55 FaultModel::FaultModel(const Params *p) : SimObject(p)

Completed in 37 milliseconds

<<1112131415

Indexes created Thu Sep 26 06:36:22 EDT 2019