Searched refs:SimObject (Results 151 - 175 of 357) sorted by relevance
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| /gem5/src/mem/cache/replacement_policies/ |
| H A D | ReplacementPolicies.py | 31 from m5.SimObject import SimObject
33 class BaseReplacementPolicy(SimObject):
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| /gem5/src/base/filters/ |
| H A D | BloomFilters.py | 31 from m5.SimObject import SimObject
33 class BloomFilterBase(SimObject):
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| /gem5/src/cpu/minor/ |
| H A D | MinorCPU.py | 48 from m5.SimObject import SimObject
56 class MinorOpClass(SimObject):
65 class MinorOpClassSet(SimObject):
74 class MinorFUTiming(SimObject):
107 class MinorFU(SimObject):
122 class MinorFUPool(SimObject):
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| /gem5/src/arch/x86/bios/ |
| H A D | IntelMP.py | 39 from m5.SimObject import SimObject
41 class X86IntelMPFloatingPointer(SimObject):
54 class X86IntelMPConfigTable(SimObject):
82 class X86IntelMPBaseConfigEntry(SimObject):
88 class X86IntelMPExtConfigEntry(SimObject):
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| H A D | acpi.cc | 54 X86ISA::ACPI::RSDP::RSDP(Params *p) : SimObject(p), oemID(p->oem_id),
59 const char * _signature, uint8_t _revision) : SimObject(p),
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| /gem5/src/mem/cache/ |
| H A D | Cache.py | 44 from m5.SimObject import SimObject
56 class WriteAllocator(SimObject):
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| /gem5/src/arch/arm/ |
| H A D | ArmISA.py | 41 from m5.SimObject import SimObject
50 class ArmISA(SimObject):
120 # This is required because in SE mode a generic System SimObject is
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| /gem5/src/dev/arm/ |
| H A D | Display.py | 39 from m5.SimObject import SimObject
42 class Display(SimObject):
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| /gem5/src/dev/x86/ |
| H A D | intdev.hh | 64 IntSlavePort(const std::string& _name, SimObject* _parent,
99 IntMasterPort(const std::string& _name, SimObject* _parent,
141 IntDevice(SimObject * parent, Tick latency = 0) :
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| /gem5/src/mem/probes/ |
| H A D | base.hh | 63 class BaseMemProbe : public SimObject
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| /gem5/src/mem/ruby/network/ |
| H A D | BasicLink.cc | 32 : SimObject(p)
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| /gem5/src/sim/power/ |
| H A D | thermal_domain.hh | 59 class ThermalDomain : public SimObject, public ThermalEntity
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| H A D | thermal_domain.cc | 54 : SimObject(p), _initTemperature(p->initial_temperature),
78 SimObject::regStats();
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| /gem5/src/sim/ |
| H A D | root.hh | 49 class Root : public SimObject
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| H A D | redirect_path.cc | 50 : SimObject(p)
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| /gem5/src/learning_gem5/part2/ |
| H A D | hello_object.cc | 37 SimObject(params),
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| /gem5/src/cpu/testers/traffic_gen/ |
| H A D | dram_gen.hh | 70 * @param obj SimObject owning this sequence generator
90 DramGen(SimObject &obj,
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| H A D | linear_gen.hh | 74 * @param obj SimObject owning this sequence generator
86 LinearGen(SimObject &obj,
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| H A D | random_gen.hh | 82 RandomGen(SimObject &obj,
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| /gem5/src/mem/cache/tags/indexing_policies/ |
| H A D | base.hh | 66 class BaseIndexingPolicy : public SimObject
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| /gem5/src/mem/qos/ |
| H A D | policy_pf.hh | 81 * the master's SimObject pointer and initial score value.
84 * @param master master's SimObject pointer to lookup.
87 void initMasterObj(const SimObject* master, const double score);
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| /gem5/util/systemc/systemc_within_gem5/systemc_simple_object/ |
| H A D | feeder.cc | 35 SimObject(params), printer(params->printer), delay(params->delay),
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| /gem5/src/cpu/kvm/ |
| H A D | BaseKvmCPU.py | 38 from m5.SimObject import *
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| /gem5/src/dev/net/ |
| H A D | etherbus.hh | 45 class EtherBus : public SimObject
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| /gem5/src/mem/ |
| H A D | tport.cc | 48 SimObject* _owner) :
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