Searched hist:9346 (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/sim/ | ||
| H A D | drain.hh | diff 9346:7a9b5e0335a6 Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Add drain methods to request additional cleanup operations This patch adds the following two methods to the Drainable base class: memWriteback() - Write back all dirty cache lines to memory using functional accesses. memInvalidate() - Invalidate memory system buffers. Dirty data won't be written back. Specifying calling memWriteback() after draining will allow us to checkpoint systems with caches. memInvalidate() can be used to drop memory system buffers in preparation for switching to an accelerated CPU model that bypasses the gem5 memory system (e.g., hardware virtualized CPUs). Note: This patch only adds the methods to Drainable, the code for flushing the TLB and the cache is committed separately. |
| /gem5/src/python/m5/ | ||
| H A D | simulate.py | diff 9346:7a9b5e0335a6 Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Add drain methods to request additional cleanup operations This patch adds the following two methods to the Drainable base class: memWriteback() - Write back all dirty cache lines to memory using functional accesses. memInvalidate() - Invalidate memory system buffers. Dirty data won't be written back. Specifying calling memWriteback() after draining will allow us to checkpoint systems with caches. memInvalidate() can be used to drop memory system buffers in preparation for switching to an accelerated CPU model that bypasses the gem5 memory system (e.g., hardware virtualized CPUs). Note: This patch only adds the methods to Drainable, the code for flushing the TLB and the cache is committed separately. |
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