Searched hist:8727 (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/cpu/o3/ | ||
| H A D | O3CPU.py | diff 8727:b3995530319f Sat Jan 28 20:09:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> O3 CPU LSQ: Implement TSO This patch makes O3's LSQ maintain total order between stores. Essentially only the store at the head of the store buffer is allowed to be in flight. Only after that store completes, the next store is issued to the memory system. By default, the x86 architecture will have TSO. |
| H A D | lsq_unit.hh | diff 8727:b3995530319f Sat Jan 28 20:09:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> O3 CPU LSQ: Implement TSO This patch makes O3's LSQ maintain total order between stores. Essentially only the store at the head of the store buffer is allowed to be in flight. Only after that store completes, the next store is issued to the memory system. By default, the x86 architecture will have TSO. |
| H A D | lsq_unit_impl.hh | diff 8727:b3995530319f Sat Jan 28 20:09:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> O3 CPU LSQ: Implement TSO This patch makes O3's LSQ maintain total order between stores. Essentially only the store at the head of the store buffer is allowed to be in flight. Only after that store completes, the next store is issued to the memory system. By default, the x86 architecture will have TSO. |
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