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| /gem5/src/arch/x86/isa/ | ||
| H A D | operands.isa | diff 8500:5bae9eee9482 Sun Aug 14 02:03:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Use IsSquashAfter if an instruction could affect fetch translation. Control register operands are set up so that writing to them is serialize after, serialize before, and non-speculative. These are probably overboard, but they should usually be safe. Unfortunately there are times when even these aren't enough. If an instruction modifies state that affects fetch, later serialized instructions which come after it might have already gone through fetch and decode by the time it commits. These instructions may have been translated incorrectly or interpretted incorrectly and need to be destroyed. This change modifies instructions which will or may have this behavior so that they use the IsSquashAfter flag when necessary. |
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