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| /gem5/src/arch/arm/ | ||
| H A D | miscregs.hh | diff 8468:5e9530779f60 Fri Jul 15 12:53:00 EDT 2011 Wade Walker <wade.walker@arm.com> ARM: Add two unimplemented miscellaneous registers. Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both registers now return values that are consistent with current ARM implementations. |
| H A D | isa.cc | diff 8468:5e9530779f60 Fri Jul 15 12:53:00 EDT 2011 Wade Walker <wade.walker@arm.com> ARM: Add two unimplemented miscellaneous registers. Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both registers now return values that are consistent with current ARM implementations. |
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