Searched hist:7646 (Results 1 - 10 of 10) sorted by relevance

/gem5/src/arch/arm/isa/templates/
H A Dmacromem.isadiff 7646:a444dbee8c07 Wed Aug 25 20:10:00 EDT 2010 Gene WU <gene.wu@arm.com> ARM: Use fewer micro-ops for register update loads if possible.

Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.
H A Dpred.isadiff 7646:a444dbee8c07 Wed Aug 25 20:10:00 EDT 2010 Gene WU <gene.wu@arm.com> ARM: Use fewer micro-ops for register update loads if possible.

Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.
H A Dmem.isadiff 7646:a444dbee8c07 Wed Aug 25 20:10:00 EDT 2010 Gene WU <gene.wu@arm.com> ARM: Use fewer micro-ops for register update loads if possible.

Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.
/gem5/src/arch/arm/isa/insts/
H A Dmem.isadiff 7646:a444dbee8c07 Wed Aug 25 20:10:00 EDT 2010 Gene WU <gene.wu@arm.com> ARM: Use fewer micro-ops for register update loads if possible.

Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.
H A Dstr.isadiff 7646:a444dbee8c07 Wed Aug 25 20:10:00 EDT 2010 Gene WU <gene.wu@arm.com> ARM: Use fewer micro-ops for register update loads if possible.

Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.
H A Dldr.isadiff 7646:a444dbee8c07 Wed Aug 25 20:10:00 EDT 2010 Gene WU <gene.wu@arm.com> ARM: Use fewer micro-ops for register update loads if possible.

Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.
H A Dmacromem.isadiff 7646:a444dbee8c07 Wed Aug 25 20:10:00 EDT 2010 Gene WU <gene.wu@arm.com> ARM: Use fewer micro-ops for register update loads if possible.

Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.
/gem5/src/arch/arm/insts/
H A Dmacromem.hhdiff 7646:a444dbee8c07 Wed Aug 25 20:10:00 EDT 2010 Gene WU <gene.wu@arm.com> ARM: Use fewer micro-ops for register update loads if possible.

Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.
H A Dmacromem.ccdiff 7646:a444dbee8c07 Wed Aug 25 20:10:00 EDT 2010 Gene WU <gene.wu@arm.com> ARM: Use fewer micro-ops for register update loads if possible.

Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.
H A Dmem.hhdiff 7646:a444dbee8c07 Wed Aug 25 20:10:00 EDT 2010 Gene WU <gene.wu@arm.com> ARM: Use fewer micro-ops for register update loads if possible.

Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.

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