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| /gem5/src/arch/x86/isa/microops/ | ||
| H A D | mediaop.isa | diff 6742:a2a79fe9655d Wed Nov 11 17:49:00 EST 2009 Vince Weaver <vince@csl.cornell.edu> X86: add ULL to 1's being shifted in 64-bit values Some of the micro-ops weren't casting 1 to ULL before shifting, which can cause problems. On the perl makerand input this caused some values to be negative that shouldn't have been. The casts are done as ULL(1) instead of 1ULL to match others in the m5 code base. |
| H A D | regop.isa | diff 6742:a2a79fe9655d Wed Nov 11 17:49:00 EST 2009 Vince Weaver <vince@csl.cornell.edu> X86: add ULL to 1's being shifted in 64-bit values Some of the micro-ops weren't casting 1 to ULL before shifting, which can cause problems. On the perl makerand input this caused some values to be negative that shouldn't have been. The casts are done as ULL(1) instead of 1ULL to match others in the m5 code base. |
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