Searched hist:6703 (Results 151 - 175 of 179) sorted by relevance
| /gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ui/ | ||
| H A D | srlw.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | sub.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | subw.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | sw.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | test.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | xor.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | xori.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/tests/test-progs/asmtest/src/riscv/isa/rv64um/ | ||
| H A D | Makefrag | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | div.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | divu.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | divuw.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | divw.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | mul.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | mulh.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | mulhsu.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | mulhu.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | mulw.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | rem.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | remu.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | remuw.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | remw.S | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/tests/test-progs/asmtest/src/riscv/ | ||
| H A D | run-tests.py | 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/util/style/ | ||
| H A D | style.py | diff 12771:75508af5d8dc Tue May 22 00:24:00 EDT 2018 Tuan Ta <qtt2@cornell.edu> tests,style: add RISC-V assembly tests This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/src/systemc/core/ | ||
| H A D | sensitivity.cc | diff 13208:6703cb024823 Fri Sep 14 23:19:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Differentiate between notifying methods and threads. The Accellera implementation notifies all types of method sensitivities first, and then notifies all the ones for threads. Change-Id: I5eda75958675ba518f008852148030e032f70d83 Reviewed-on: https://gem5-review.googlesource.com/c/12807 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
| H A D | sensitivity.hh | diff 13208:6703cb024823 Fri Sep 14 23:19:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Differentiate between notifying methods and threads. The Accellera implementation notifies all types of method sensitivities first, and then notifies all the ones for threads. Change-Id: I5eda75958675ba518f008852148030e032f70d83 Reviewed-on: https://gem5-review.googlesource.com/c/12807 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
Completed in 48 milliseconds