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| /gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/ | ||
| H A D | conditional_move.py | diff 6482:e4b8ec60fd4b Sat Aug 08 20:23:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make not taken conditional moves leave the destination alone. Adjust CMOVcc. The manuals from both AMD and Intel say that when writing to a 32 bit destination in 64 bit mode, the upper 32 bits of the register are filled with zeros. They also both say that the CMOV instructions leave their destination alone when their condition fails. Unfortunately, it seems that CMOV will zero extend its destination register whether or not it was supposed to actually do a move on both platforms. This seems to be the only case where this happens, but it would be hard to say for sure. |
| /gem5/src/arch/x86/isa/microops/ | ||
| H A D | regop.isa | diff 6482:e4b8ec60fd4b Sat Aug 08 20:23:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make not taken conditional moves leave the destination alone. Adjust CMOVcc. The manuals from both AMD and Intel say that when writing to a 32 bit destination in 64 bit mode, the upper 32 bits of the register are filled with zeros. They also both say that the CMOV instructions leave their destination alone when their condition fails. Unfortunately, it seems that CMOV will zero extend its destination register whether or not it was supposed to actually do a move on both platforms. This seems to be the only case where this happens, but it would be hard to say for sure. |
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