Searched hist:6441 (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/arch/x86/isa/insts/x87/control/ | ||
| H A D | save_and_restore_x87_environment.py | diff 12368:511bd7aa22d1 Tue Dec 05 20:49:00 EST 2017 Gabe Black <gabeblack@google.com> x86: Split apart x87's FSW and TOP, and add a missing break. The FSW and TOP values are technically part of the same register, but they have very different behaviors. One of them can be renamed and float along without affecting global state, while the other requires serialization. They just need to *look* like the same register when read by the user. Also, there was a missing break in setMiscRegNoEffect. Change-Id: If58de0f566f65068208240f4001209fb9e1826d6 Reviewed-on: https://gem5-review.googlesource.com/6441 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> |
| /gem5/src/arch/x86/ | ||
| H A D | isa.cc | diff 12368:511bd7aa22d1 Tue Dec 05 20:49:00 EST 2017 Gabe Black <gabeblack@google.com> x86: Split apart x87's FSW and TOP, and add a missing break. The FSW and TOP values are technically part of the same register, but they have very different behaviors. One of them can be renamed and float along without affecting global state, while the other requires serialization. They just need to *look* like the same register when read by the user. Also, there was a missing break in setMiscRegNoEffect. Change-Id: If58de0f566f65068208240f4001209fb9e1826d6 Reviewed-on: https://gem5-review.googlesource.com/6441 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> |
| /gem5/src/arch/x86/isa/microops/ | ||
| H A D | regop.isa | diff 6441:801f1fc07a58 Wed Aug 05 05:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix the carry flag for shl. |
Completed in 21 milliseconds