Searched hist:6401 (Results 1 - 6 of 6) sorted by relevance
/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64i/ | ||
H A D | insttest | diff 12428:ddc6b7179c81 Sat Dec 02 00:58:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Make use of ImmOp's polymorphism This patch makes use of ImmOp's polymorphism to remove unnecessary casting from the implementations of arithmetic instructions with immediate operands and to remove the CUIOp format by combining it with the CIOp format (compressed arithmetic instructions with immediate operands). Interestingly, RISC-V specifies that instructions with unsigned immediate operands still need to sign-extend the immediates from 12 (or 20) bits to 64 bits, so that is left alone. Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16 Reviewed-on: https://gem5-review.googlesource.com/6401 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tuan Ta <qtt2@cornell.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
/gem5/tests/test-progs/insttest/src/riscv/ | ||
H A D | rv64i.cpp | diff 12428:ddc6b7179c81 Sat Dec 02 00:58:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Make use of ImmOp's polymorphism This patch makes use of ImmOp's polymorphism to remove unnecessary casting from the implementations of arithmetic instructions with immediate operands and to remove the CUIOp format by combining it with the CIOp format (compressed arithmetic instructions with immediate operands). Interestingly, RISC-V specifies that instructions with unsigned immediate operands still need to sign-extend the immediates from 12 (or 20) bits to 64 bits, so that is left alone. Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16 Reviewed-on: https://gem5-review.googlesource.com/6401 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tuan Ta <qtt2@cornell.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
/gem5/src/arch/riscv/isa/formats/ | ||
H A D | compressed.isa | diff 12428:ddc6b7179c81 Sat Dec 02 00:58:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Make use of ImmOp's polymorphism This patch makes use of ImmOp's polymorphism to remove unnecessary casting from the implementations of arithmetic instructions with immediate operands and to remove the CUIOp format by combining it with the CIOp format (compressed arithmetic instructions with immediate operands). Interestingly, RISC-V specifies that instructions with unsigned immediate operands still need to sign-extend the immediates from 12 (or 20) bits to 64 bits, so that is left alone. Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16 Reviewed-on: https://gem5-review.googlesource.com/6401 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tuan Ta <qtt2@cornell.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
H A D | standard.isa | diff 12428:ddc6b7179c81 Sat Dec 02 00:58:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Make use of ImmOp's polymorphism This patch makes use of ImmOp's polymorphism to remove unnecessary casting from the implementations of arithmetic instructions with immediate operands and to remove the CUIOp format by combining it with the CIOp format (compressed arithmetic instructions with immediate operands). Interestingly, RISC-V specifies that instructions with unsigned immediate operands still need to sign-extend the immediates from 12 (or 20) bits to 64 bits, so that is left alone. Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16 Reviewed-on: https://gem5-review.googlesource.com/6401 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tuan Ta <qtt2@cornell.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
/gem5/src/arch/riscv/isa/ | ||
H A D | decoder.isa | diff 12428:ddc6b7179c81 Sat Dec 02 00:58:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Make use of ImmOp's polymorphism This patch makes use of ImmOp's polymorphism to remove unnecessary casting from the implementations of arithmetic instructions with immediate operands and to remove the CUIOp format by combining it with the CIOp format (compressed arithmetic instructions with immediate operands). Interestingly, RISC-V specifies that instructions with unsigned immediate operands still need to sign-extend the immediates from 12 (or 20) bits to 64 bits, so that is left alone. Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16 Reviewed-on: https://gem5-review.googlesource.com/6401 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tuan Ta <qtt2@cornell.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
/gem5/src/arch/arm/ | ||
H A D | isa.hh | diff 6401:4e9d4c206930 Mon Jul 27 03:52:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Initialize the CPSR so that we're in user mode. |
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