Searched hist:5363 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/arm/isa/insts/
H A Dmisc64.isadiff 12261:88f4f45ec80c Mon Oct 23 05:54:00 EDT 2017 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Dsb instruction shouldn't flush the pipeline

DSB Instruction shouldn't flush the pipeline, hence the IsSquashAfter
attribute will be removed for either the 32 and 64 bit version.

Change-Id: I98b2b8bc78aa28445ed1a9b5f34645f8d71616ad
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5363
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dmisc.isadiff 12261:88f4f45ec80c Mon Oct 23 05:54:00 EDT 2017 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Dsb instruction shouldn't flush the pipeline

DSB Instruction shouldn't flush the pipeline, hence the IsSquashAfter
attribute will be removed for either the 32 and 64 bit version.

Change-Id: I98b2b8bc78aa28445ed1a9b5f34645f8d71616ad
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5363
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/cpu/o3/
H A Dcpu.ccdiff 5363:c474cb7a2b9c Wed Feb 27 16:53:00 EST 2008 Korey Sewell <ksewell@umich.edu> Fix Load/Store Queue squashing after a SMT thread is removed but ensuring
you are squashing from the current instruction # causing the thread exit.

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