Searched hist:5319 (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/mem/ | ||
| H A D | packet.cc | diff 5319:13cb690ba6d6 Wed Jan 02 18:22:00 EST 2008 Steve Reinhardt <stever@gmail.com> Add ReadRespWithInvalidate to handle multi-level coherence situation where we defer a response to a read from a far-away cache A, then later defer a ReadExcl from a cache B on the same bus as us. We'll assert MemInhibit in both cases, but in the latter case MemInhibit will keep the invalidation from reaching cache A. This special response tells cache A that it gets the block to satisfy its read, but must immediately invalidate it. |
| H A D | packet.hh | diff 5319:13cb690ba6d6 Wed Jan 02 18:22:00 EST 2008 Steve Reinhardt <stever@gmail.com> Add ReadRespWithInvalidate to handle multi-level coherence situation where we defer a response to a read from a far-away cache A, then later defer a ReadExcl from a cache B on the same bus as us. We'll assert MemInhibit in both cases, but in the latter case MemInhibit will keep the invalidation from reaching cache A. This special response tells cache A that it gets the block to satisfy its read, but must immediately invalidate it. |
| /gem5/src/mem/cache/ | ||
| H A D | cache.hh | diff 5319:13cb690ba6d6 Wed Jan 02 18:22:00 EST 2008 Steve Reinhardt <stever@gmail.com> Add ReadRespWithInvalidate to handle multi-level coherence situation where we defer a response to a read from a far-away cache A, then later defer a ReadExcl from a cache B on the same bus as us. We'll assert MemInhibit in both cases, but in the latter case MemInhibit will keep the invalidation from reaching cache A. This special response tells cache A that it gets the block to satisfy its read, but must immediately invalidate it. |
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