Searched hist:5242 (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/base/ | ||
| H A D | addr_range_map.hh | diff 12777:70526b89f66e Wed Oct 18 22:55:00 EDT 2017 Gabe Black <gabeblack@google.com> base: Build caching into the AddrRangeMap class Rather than have each consumer of the AddrRangeMap implement caching lookups on their own, this change adds a centralized mechanism to the AddrRangeMap class itself. Some benefits of this approach are that the cache handles deleted entries correctly/automatically, the cache is maintained by adding/removing entries from a linked list rather than moving elements in an array and checking valid bits, and it's easy to enable in places which might otherwise not bother with caching. The amount of caching is tunable to balance overhead with improved lookup performance. Change-Id: Ic25997e23de4eea501e47f039bb52ed0502c58d2 Reviewed-on: https://gem5-review.googlesource.com/5242 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
| /gem5/src/arch/x86/ | ||
| H A D | tlb.hh | diff 5242:280a99136427 Mon Nov 12 17:39:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement tlb invalidation and make it happen some of the times it should. |
| H A D | tlb.cc | diff 5242:280a99136427 Mon Nov 12 17:39:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement tlb invalidation and make it happen some of the times it should. |
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