Searched hist:5176 (Results 1 - 6 of 6) sorted by relevance
| /gem5/src/arch/x86/isa/insts/general_purpose/flags/ | ||
| H A D | push_and_pop.py | diff 5176:43fb805e1b85 Sun Oct 21 21:45:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start using the stupd microop, and update statistics accordingly. |
| /gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/ | ||
| H A D | call.py | diff 5176:43fb805e1b85 Sun Oct 21 21:45:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start using the stupd microop, and update statistics accordingly. |
| /gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/ | ||
| H A D | stack_operations.py | diff 5176:43fb805e1b85 Sun Oct 21 21:45:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start using the stupd microop, and update statistics accordingly. |
| /gem5/src/mem/ruby/slicc_interface/ | ||
| H A D | RubySlicc_ComponentMapping.hh | diff 10008:5176f0a71e56 Sat Jan 04 01:03:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: add a three level MESI protocol. The first two levels (L0, L1) are private to the core, the third level (L2)is possibly shared. The protocol supports clustered designs. For example, one can have two sets of two cores. Each core has an L0 and L1 cache. There are two L2 controllers where each set accesses only one of the L2 controllers. |
| /gem5/configs/ruby/ | ||
| H A D | MESI_Three_Level.py | 10008:5176f0a71e56 Sat Jan 04 01:03:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: add a three level MESI protocol. The first two levels (L0, L1) are private to the core, the third level (L2)is possibly shared. The protocol supports clustered designs. For example, one can have two sets of two cores. Each core has an L0 and L1 cache. There are two L2 controllers where each set accesses only one of the L2 controllers. |
| /gem5/src/mem/slicc/symbols/ | ||
| H A D | StateMachine.py | diff 10008:5176f0a71e56 Sat Jan 04 01:03:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: add a three level MESI protocol. The first two levels (L0, L1) are private to the core, the third level (L2)is possibly shared. The protocol supports clustered designs. For example, one can have two sets of two cores. Each core has an L0 and L1 cache. There are two L2 controllers where each set accesses only one of the L2 controllers. |
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