Searched hist:5042 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/x86/isa/microops/
H A Dregop.isadiff 5042:bc2c08abe249 Wed Sep 05 02:22:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix a corner case where mul would overwrite an original register value it still needed.
/gem5/src/mem/cache/
H A Dcache.hhdiff 12343:51ae6d08466f Fri Sep 29 10:24:00 EDT 2017 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Add support for checking whether a cache is busy

This changeset adds support for checking whether the cache is
currently busy and a timing request would be rejected.

Change-Id: I5e37b011b2387b1fa1c9e687b9be545f06ffb5f5
Reviewed-on: https://gem5-review.googlesource.com/5042
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dcache.ccdiff 12343:51ae6d08466f Fri Sep 29 10:24:00 EDT 2017 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Add support for checking whether a cache is busy

This changeset adds support for checking whether the cache is
currently busy and a timing request would be rejected.

Change-Id: I5e37b011b2387b1fa1c9e687b9be545f06ffb5f5
Reviewed-on: https://gem5-review.googlesource.com/5042
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

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