Searched hist:5040 (Results 1 - 6 of 6) sorted by relevance

/gem5/src/mem/
H A DXBar.pydiff 12341:6eebba99d117 Tue May 31 08:43:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: Add the notion of point of unification in the coherent xbar

The point of unification is the first crossbar at which the
instruction cache, the data cache and the translation table walks of
the core are guaranteed to see the same copy of a memory location.

Change-Id: Ica79b34c8ed4f1a8f2379748e8520a8f8afffa90
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5040
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dcoherent_xbar.hhdiff 12341:6eebba99d117 Tue May 31 08:43:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: Add the notion of point of unification in the coherent xbar

The point of unification is the first crossbar at which the
instruction cache, the data cache and the translation table walks of
the core are guaranteed to see the same copy of a memory location.

Change-Id: Ica79b34c8ed4f1a8f2379748e8520a8f8afffa90
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5040
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dcoherent_xbar.ccdiff 12341:6eebba99d117 Tue May 31 08:43:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: Add the notion of point of unification in the coherent xbar

The point of unification is the first crossbar at which the
instruction cache, the data cache and the translation table walks of
the core are guaranteed to see the same copy of a memory location.

Change-Id: Ica79b34c8ed4f1a8f2379748e8520a8f8afffa90
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5040
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/arch/x86/isa/microops/
H A Dbase.isadiff 5040:126e4510b5bb Sat Sep 01 01:28:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Major rework of how regop microops are generated.
The new implementation uses metaclass, and gives a lot more precise control
with a lot less verbosity. The flags/no flags reg/imm variants are all handled
by the same python class now which supplies a constructor to the right C++
class based on context.
H A Dregop.isadiff 5040:126e4510b5bb Sat Sep 01 01:28:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Major rework of how regop microops are generated.
The new implementation uses metaclass, and gives a lot more precise control
with a lot less verbosity. The flags/no flags reg/imm variants are all handled
by the same python class now which supplies a constructor to the right C++
class based on context.
/gem5/src/arch/x86/isa/
H A Dmacroop.isadiff 5040:126e4510b5bb Sat Sep 01 01:28:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Major rework of how regop microops are generated.
The new implementation uses metaclass, and gives a lot more precise control
with a lot less verbosity. The flags/no flags reg/imm variants are all handled
by the same python class now which supplies a constructor to the right C++
class based on context.

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