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/gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/
H A Dconfig.inidiff 10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes

Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
/gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/
H A Dconfig.inidiff 10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes

Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/
H A Dsimoutdiff 10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes

Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
/gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing/
H A Dconfig.inidiff 10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes

Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
/gem5/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/
H A Dstats.txtdiff 10093:9c55c0214404 Mon Feb 24 21:50:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to c0db268f811b
diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
/gem5/tests/quick/se/00.hello/ref/x86/linux/o3-timing/
H A Dconfig.inidiff 10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes

Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
/gem5/src/cpu/pred/
H A Dbtb.hhdiff 7720:65d338a8dba4 Sun Oct 31 03:07:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.



This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.


PC type:

Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.

These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.

Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.


Advancing the PC:

The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.

One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.


Variable length instructions:

To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.


ISA parser:

To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.


Return address stack:

The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.


Change in stats:

There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.


TODO:

Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.
6226:f1076450ab2b Fri Jun 05 00:50:00 EDT 2009 Nathan Binkert <nate@binkert.org> move: put predictor includes and cc files into the same place
H A Dbpred_unit.ccdiff 13831:4fba790d88be Wed Mar 06 10:50:00 EST 2019 Andrea Mondelli <Andrea.Mondelli@ucf.edu> misc: Removed inconsistency in O3* debug msgs

Added consistency in the DEBUG message form, to allow a better parsing.
Fixed sn/tid type parameter.
Removed some annoying newlines

Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17248
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
diff 10244:d2deb51a4abf Mon Jun 30 13:50:00 EDT 2014 Anthony Gutierrez <atgutier@umich.edu> cpu: implement a bi-mode branch predictor
/gem5/src/dev/arm/
H A Dtimer_sp804.ccdiff 12772:362544959c40 Mon Jun 04 12:50:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> dev-arm: Fix the address range for some I/O devices

Previously, many devices were incorrecty configured to respond to an
address range of size 0xfff. This changes fixes this and sets it to
0x1000.

Change-Id: I4b027a27adf60ceae4859e287d7f34443b398752
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11116
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
H A DGic.pydiff 14152:72230d99538e Fri Aug 09 10:50:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Use FdtState to generate GIC properites

Rather than hardcoding property values, we use a FdtState variable, so
that it is possible to retrieve them from an external object.

Change-Id: Ifd90814b03c68a7f55ef3be6123dcfee5e1de568
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20051
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff 13014:a4f71c3dc602 Thu Aug 30 09:50:00 EDT 2018 Ciro Santilli <ciro.santilli@arm.com> dev-arm: rename Pl390 to GicV2

The Pl390 model has evolved and acquired a lot of the features from GICv2,
which means that the name is no longer appropriate. Rename it to GICv2
since this is more representative of the supported features.

GICv2 is backwards compatible with the older Pl390, so we decided to
simply rename the class to represent both GICv2 and older interfaces such
as the instead of creating a new separate one.

Change-Id: I1c05fba8b3cb5841c66480e9f05b8c873eba3229
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12492
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff 13013:b204ddd2b986 Thu Aug 30 09:50:00 EDT 2018 Ciro Santilli <ciro.santilli@arm.com> dev-arm: improve Pl390 parameters

Remove default dist_addr and cpu_addr register addresses since those are
purely platform specific.

Parametrize the cpu_size parameter. RealViewPBX has the Gic CPU and
distributor base too close for the newer CPU size of 0x2000, leading to
overlap.

This was introduced in I90a9f669a46a37d79c6cc542087cf91f2044f104 and makes
using RealViewPBX fail with:

fatal: system.membus has two ports responding within range
[0x1f000100 : 0x1f0020ff]:
system.realview.gic.pio
system.realview.gic.pio

Change-Id: Ic6c0e6b3d4705ff369eb739d54a1173a47819b7d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12491
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dpl011.ccdiff 12772:362544959c40 Mon Jun 04 12:50:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> dev-arm: Fix the address range for some I/O devices

Previously, many devices were incorrecty configured to respond to an
address range of size 0xfff. This changes fixes this and sets it to
0x1000.

Change-Id: I4b027a27adf60ceae4859e287d7f34443b398752
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11116
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
/gem5/src/cpu/simple/
H A DAtomicSimpleCPU.pydiff 8926:570b44fe6e04 Tue Apr 03 03:50:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Atomic: Remove the physmem_port and access memory directly

This patch removes the physmem_port from the Atomic CPU and instead
uses the system pointer to access the physmem when using the fastmem
option. The system already keeps track of the physmem and the valid
memory address ranges, and with this patch we merely make use of that
existing functionality. As a result of this change, the overloaded
getMasterPort in the Atomic CPU can be removed, thus unifying the CPUs.
diff 5536:17c0c17726ff Mon Aug 18 13:50:00 EDT 2008 Richard Strong<rstrong@hp.com> Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its
python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.
/gem5/src/arch/mips/
H A Disa.ccdiff 13831:4fba790d88be Wed Mar 06 10:50:00 EST 2019 Andrea Mondelli <Andrea.Mondelli@ucf.edu> misc: Removed inconsistency in O3* debug msgs

Added consistency in the DEBUG message form, to allow a better parsing.
Fixed sn/tid type parameter.
Removed some annoying newlines

Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17248
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
diff 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
/gem5/src/arch/x86/
H A Dsystem.ccdiff 7720:65d338a8dba4 Sun Oct 31 03:07:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.



This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.


PC type:

Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.

These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.

Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.


Advancing the PC:

The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.

One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.


Variable length instructions:

To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.


ISA parser:

To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.


Return address stack:

The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.


Change in stats:

There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.


TODO:

Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.
diff 5615:1c4b9b1aa500 Fri Oct 10 06:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Turn SMBios structures into simobjects.
diff 5612:1bd333953e49 Fri Oct 10 06:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Move the smbios objects into a folder for BIOS objects.
/gem5/src/sim/
H A Dstat_control.ccdiff 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
diff 7822:fc475ac7d2a4 Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> stats: rename StatEvent() function to schedStatEvent().
This follows the style rules and is more descriptive.
H A Dsimulate.ccdiff 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
diff 7822:fc475ac7d2a4 Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> stats: rename StatEvent() function to schedStatEvent().
This follows the style rules and is more descriptive.
H A Dsim_exit.hhdiff 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
diff 7819:afe8476ee9e9 Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> pseudoinst: get rid of mainEventQueue references.
Avoid direct references to mainEventQueue in pseudo-insts
by indirecting through associated CPU object.
Made exitSimLoop() more flexible to enable some of these.
/gem5/src/arch/arm/insts/
H A Dmacromem.hhdiff 7720:65d338a8dba4 Sun Oct 31 03:07:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.



This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.


PC type:

Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.

These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.

Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.


Advancing the PC:

The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.

One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.


Variable length instructions:

To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.


ISA parser:

To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.


Return address stack:

The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.


Change in stats:

There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.


TODO:

Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.
diff 7615:50f6494d9b55 Mon Aug 23 12:18:00 EDT 2010 Min Kyu Jeong <minkyu.jeong@arm.com> ARM: Improve printing of uop disassembly.
H A Dmacromem.ccdiff 9368:3cd40209af8d Wed Dec 12 10:50:00 EST 2012 Nathanael Premillieu <nathanael.premillieu@irisa.fr> arm: set movret_uop as conditional or unconditional control
A flag was missing for the movret_uop microop instruction. This patch adds
that flag when the instruction is used, not directly in the constructor of
the instruction.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
diff 7615:50f6494d9b55 Mon Aug 23 12:18:00 EDT 2010 Min Kyu Jeong <minkyu.jeong@arm.com> ARM: Improve printing of uop disassembly.
/gem5/src/arch/arm/isa/formats/
H A Dmem.isadiff 7124:50d26210c812 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode 16 bit thumb register addressed memory instructions.
diff 7045:e21fe6a62b1c Tue Mar 23 11:50:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> cpu: fix exec tracing memory corruption bug
Accessing traceData (to call setAddress() and/or setData())
after initiating a timing translation was causing crashes,
since a failed translation could delete the traceData
object before returning.

It turns out that there was never a need to access traceData
after initiating the translation, as the traced data was
always available earlier; this ordering was merely
historical. Furthermore, traceData->setAddress() and
traceData->setData() were being called both from the CPU
model and the ISA definition, often redundantly.

This patch standardizes all setAddress and setData calls
for memory instructions to be in the CPU models and not
in the ISA definition. It also moves those calls above
the translation calls to eliminate the crashes.
H A Ddata.isadiff 14031:7edee4296f90 Fri May 31 03:50:00 EDT 2019 Chun-Chen TK Hsu <chunchenhsu@google.com> arm: Fix decoding of CRC32 instructions in thumb32

The CRC32 and CRC32C instructions are incorrectly decoded in thumb32
mode according to the latest manual:
https://developer.arm.com/docs/ddi0597/latest/top-level-encodings-for-t32/16-bit#dpint_2r

Change-Id: I9c6684f1ec7fe14d3b4cdf13f117a9819e046578
Signed-off-by: Chun-Chen TK Hsu
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19028
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff 13354:c1bdac713ae5 Wed Sep 19 10:50:00 EDT 2018 Ciro Santilli <ciro.santilli@arm.com> arm: update hint instruction decoding to match ARMv8.5

This fixes:

- unallocated hints that have since been allocated
- unallocated and unimplemented hint instructions being treated as
Unknown instead of the correct NOP
- missing encoding for DBG on A32

Unallocated and unimplemented hints give a warning if executed.

The most important fix was for the CSDB Spectre mitigation
instruction, which was added recently and previously unallocated and
treated as Unknown.

The Linux kernel v4.18 ARMv7 uses CSDB it and boot would
fail with "undefined instruction" since Linux commit
1d4238c56f9816ce0f9c8dbe42d7f2ad81cb6613

Change-Id: I283da3f08a9af4148edc6fb3ca2930cbb97126b8
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13475
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/base/
H A Dtrace.hhdiff 10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model

This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).

The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).

Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.

Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.

Minor is faster than the o3 model. Sample results:

Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
diff 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
/gem5/system/alpha/console/
H A DMakefilediff 8003:7408e4b599ae Sun Aug 01 00:50:00 EDT 2004 Ali Saidi <saidi@eecs.umich.edu> changed to generate tlaser and tsunami console code at different
addresses so the uncachable bit is set for tsunami.

console/Makefile:
console/console.c:
changed to generate tlaser and tsunami console code at different addresses
/gem5/src/arch/arm/isa/decoder/
H A Dthumb.isadiff 7124:50d26210c812 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode 16 bit thumb register addressed memory instructions.
/gem5/src/arch/sparc/
H A Dasi.hhdiff 3825:9b5e6c4d3ecb Thu Dec 07 18:50:00 EST 2006 Ali Saidi <saidi@eecs.umich.edu> get legion/m5 to first tlb miss fault

src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
add sparc error asi
src/arch/sparc/faults.cc:
put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
add sparc error register code that just does nothing
fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
fix implementation of HPSTATE write
src/cpu/exetrace.cc:
let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
add l2 error status register fake devices

Completed in 172 milliseconds

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