Searched hist:4581 (Results 1 - 4 of 4) sorted by relevance

/gem5/src/arch/x86/isa/microops/
H A Dlimmop.isadiff 4581:23166f771fa4 Mon Jun 18 10:15:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add in incomplete pick and merge functions which read and write pieces of registers, and fill out microcode disassembly.
H A Dregop.isadiff 4581:23166f771fa4 Mon Jun 18 10:15:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add in incomplete pick and merge functions which read and write pieces of registers, and fill out microcode disassembly.
/gem5/src/arch/x86/
H A Disa_traits.hhdiff 4581:23166f771fa4 Mon Jun 18 10:15:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add in incomplete pick and merge functions which read and write pieces of registers, and fill out microcode disassembly.
/gem5/src/arch/x86/isa/decoder/
H A Dtwo_byte_opcodes.isadiff 12170:efbf270e389d Thu Aug 24 20:06:00 EDT 2017 Gabe Black <gabeblack@google.com> x86: Use the new CondInst format for moves to/from control registers.

The condition is whether the control register index is valid.

Change-Id: I8a225fcfd4955032b5bbf7d3392ee5bcc7d6bc64
Reviewed-on: https://gem5-review.googlesource.com/4581
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

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