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/gem5/src/arch/hsail/
H A Dgpu_isa.hhdiff 13593:4164fea26cbb Mon Nov 19 22:03:00 EST 2018 Gabe Black <gabeblack@google.com> hsail: Remove the MiscReg type.

It has been replaced by the ISA agnostic RegVal.

Change-Id: I563ea3852e37b5c1cf51eb0ac9a6f2a827ba89cf
Reviewed-on: https://gem5-review.googlesource.com/c/14464
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/arch/sparc/
H A Dprocess.ccdiff 4164:c4a2eeafec9e Thu Mar 08 00:29:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Fix up the SPARC initial stack frame to match an actual 32 bit process.
/gem5/src/cpu/simple/
H A Dbase.ccdiff 5310:4164e6bfcc8a Sun Dec 16 03:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> CPU: Update where the simple cpus read their cpu id from the thread context to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations.
H A Dtiming.ccdiff 5310:4164e6bfcc8a Sun Dec 16 03:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> CPU: Update where the simple cpus read their cpu id from the thread context to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations.
H A Datomic.ccdiff 5310:4164e6bfcc8a Sun Dec 16 03:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> CPU: Update where the simple cpus read their cpu id from the thread context to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations.

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