Searched hist:3900 (Results 1 - 3 of 3) sorted by relevance
/gem5/src/dev/arm/ | ||
H A D | vgic.hh | diff 12092:9bb326b4661d Thu Jun 29 10:12:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> arm: Fix memleak in VGic by adding destructor Change-Id: I864b5d9ed655cc52e440e2eb54987e8ff9a73296 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3900 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | vgic.cc | diff 12092:9bb326b4661d Thu Jun 29 10:12:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> arm: Fix memleak in VGic by adding destructor Change-Id: I864b5d9ed655cc52e440e2eb54987e8ff9a73296 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3900 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/arch/sparc/isa/ | ||
H A D | decoder.isa | diff 3900:e233f57b5afe Wed Jan 10 22:19:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> bug fixes to get us to 145m instructions src/arch/sparc/intregfile.cc: some checks to make sure that the cwp and global register flattening stuff is working. These things have caught a couple of bugs so I think it would be good to keep them around at least for now src/arch/sparc/isa/decoder.isa: fix smul instruction to write Y correctly src/arch/sparc/miscregfile.cc: legion always returns du and dl set, so we need to emulate that for now at least |
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