Searched hist:3262 (Results 1 - 5 of 5) sorted by relevance

/gem5/src/dev/arm/
H A Dtimer_a9global.hh12077:3c014d139dc7 Thu Feb 23 15:51:00 EST 2017 Gedare Bloom <gedare@rtems.org> dev, arm: add a9mpcore global timer device

Change-Id: I6d8a5e3795291b2a4cce022f555cf4b04f997538
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3262
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dtimer_a9global.cc12077:3c014d139dc7 Thu Feb 23 15:51:00 EST 2017 Gedare Bloom <gedare@rtems.org> dev, arm: add a9mpcore global timer device

Change-Id: I6d8a5e3795291b2a4cce022f555cf4b04f997538
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3262
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A DSConscriptdiff 12077:3c014d139dc7 Thu Feb 23 15:51:00 EST 2017 Gedare Bloom <gedare@rtems.org> dev, arm: add a9mpcore global timer device

Change-Id: I6d8a5e3795291b2a4cce022f555cf4b04f997538
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3262
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A DRealView.pydiff 12077:3c014d139dc7 Thu Feb 23 15:51:00 EST 2017 Gedare Bloom <gedare@rtems.org> dev, arm: add a9mpcore global timer device

Change-Id: I6d8a5e3795291b2a4cce022f555cf4b04f997538
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3262
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/mem/
H A Dpacket.ccdiff 3262:5f96609a30ef Wed Oct 11 18:28:00 EDT 2006 Ron Dreslinski <rdreslin@umich.edu> More cache fixes. Atomic coherence now works as well.

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
Debug output.
Clean up memleak in atomic mode.
Set hitLatency.
Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
Add command strings for new commands
src/python/m5/objects/MemTest.py:
Add param to test atomic memory.

Completed in 60 milliseconds