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/gem5/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/
H A Dconfig.jsondiff 12062:d6ee16239a26 Wed May 31 18:49:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> tests: Update RISC-V hello test and stats

Update the "Hello, world!" executable for RISC-V to use the latest GNU
Linux toolchain and fix the stats accordingly.

Change-Id: I5ff3d7f4bb41b10170038b8c07492f15bb54a022
Reviewed-on: https://gem5-review.googlesource.com/3560
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
H A Dsimoutdiff 12062:d6ee16239a26 Wed May 31 18:49:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> tests: Update RISC-V hello test and stats

Update the "Hello, world!" executable for RISC-V to use the latest GNU
Linux toolchain and fix the stats accordingly.

Change-Id: I5ff3d7f4bb41b10170038b8c07492f15bb54a022
Reviewed-on: https://gem5-review.googlesource.com/3560
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
H A Dsimerrdiff 12062:d6ee16239a26 Wed May 31 18:49:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> tests: Update RISC-V hello test and stats

Update the "Hello, world!" executable for RISC-V to use the latest GNU
Linux toolchain and fix the stats accordingly.

Change-Id: I5ff3d7f4bb41b10170038b8c07492f15bb54a022
Reviewed-on: https://gem5-review.googlesource.com/3560
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/mem/ruby/network/garnet2.0/
H A DGarnetLink.hhdiff 11715:31b2c4b52047 Mon Nov 21 15:41:00 EST 2016 Jieming Yin <jieming.yin@amd.com> ruby: Fix potential bugs in garnet2.0

1. Delete unused variable from struct LinkEntry
2. Correct GarnetExtLink and GarnetIntLink inheritance
/gem5/src/systemc/ext/core/
H A Dsc_module_name.hhdiff 12863:ed8c2541cb30 Thu May 31 21:42:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Construct and manage a module name stack.

Change-Id: I5f7f64d6c3d7e08ec6d2529f3c5d84fbfc2c421b
Reviewed-on: https://gem5-review.googlesource.com/10850
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/cpu/testers/garnet_synthetic_traffic/
H A DSConscriptdiff 12892:796175b0e2dc Thu Feb 15 17:31:00 EST 2018 Brandon Potter <brandon.potter@amd.com> scons,ruby: do not generate unnecessary files

Do not generate garnet tester file or Ruby debug headers without a Ruby
protocol (i.e. PROTOCOL=None). It makes no sense to include these files
into the build when there will be no protocol to utilize them.

Change-Id: I8db4dd532f60008217a10c88a2e089f85df9d104
Reviewed-on: https://gem5-review.googlesource.com/8381
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/mem/cache/compressors/
H A Dcpack.cc14089:fe1e5813d62c Wed May 30 08:31:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Create CPack compressor

Implementation of C-Pack, as described in "C-Pack: A High-
Performance Microprocessor Cache Compression Algorithm".

C-Pack uses pattern matching schemes to detect and compress
frequently appearing data patterns. As in the original paper,
it divides the input in 32-bit words, and uses 6 patterns to
match with its dictionary.

For the patterns, each letter represents a byte: Z is a null
byte, M is a dictionary match, X is a new value. The patterns
are ZZZZ, XXXX, MMMM, MMXX, ZZZX, MMMX.

Change-Id: I2efc9db2c862620dcc1155300e39be558f9017e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11105
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A Dcpack.hh14089:fe1e5813d62c Wed May 30 08:31:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Create CPack compressor

Implementation of C-Pack, as described in "C-Pack: A High-
Performance Microprocessor Cache Compression Algorithm".

C-Pack uses pattern matching schemes to detect and compress
frequently appearing data patterns. As in the original paper,
it divides the input in 32-bit words, and uses 6 patterns to
match with its dictionary.

For the patterns, each letter represents a byte: Z is a null
byte, M is a dictionary match, X is a new value. The patterns
are ZZZZ, XXXX, MMMM, MMXX, ZZZX, MMMX.

Change-Id: I2efc9db2c862620dcc1155300e39be558f9017e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11105
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/tests/test-progs/chdir-print/
H A DMakefile14137:31b40f827718 Mon Mar 11 14:30:00 EDT 2019 Brandon Potter <brandon.potter@amd.com> sim-se, tests: add a new sim-se test

This changeset adds a test to check the redirection features
added in faux-filesystem changeset. The test contains a
"chdir" system call to "/proc" which should be redirected to
"$(gem5-dir)/m5out/fs/proc" (as specified by the config files).

After "chdir", the test subsequently outputs the "/proc/cpuinfo"
file which should output a configuration of a fake cpu with
values set by a Python configuration file.

Note, the test will call "clone" once. To avoid a runtime error,
make sure that you run this test with "-n2" supplied to the
"config/example/se.py" script.

Change-Id: I505b046b7a4feddfa93a6ef0f0773ac43078cc94
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17112
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
H A DREADME.txt14137:31b40f827718 Mon Mar 11 14:30:00 EDT 2019 Brandon Potter <brandon.potter@amd.com> sim-se, tests: add a new sim-se test

This changeset adds a test to check the redirection features
added in faux-filesystem changeset. The test contains a
"chdir" system call to "/proc" which should be redirected to
"$(gem5-dir)/m5out/fs/proc" (as specified by the config files).

After "chdir", the test subsequently outputs the "/proc/cpuinfo"
file which should output a configuration of a fake cpu with
values set by a Python configuration file.

Note, the test will call "clone" once. To avoid a runtime error,
make sure that you run this test with "-n2" supplied to the
"config/example/se.py" script.

Change-Id: I505b046b7a4feddfa93a6ef0f0773ac43078cc94
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17112
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
H A Dchdir-print.c14137:31b40f827718 Mon Mar 11 14:30:00 EDT 2019 Brandon Potter <brandon.potter@amd.com> sim-se, tests: add a new sim-se test

This changeset adds a test to check the redirection features
added in faux-filesystem changeset. The test contains a
"chdir" system call to "/proc" which should be redirected to
"$(gem5-dir)/m5out/fs/proc" (as specified by the config files).

After "chdir", the test subsequently outputs the "/proc/cpuinfo"
file which should output a configuration of a fake cpu with
values set by a Python configuration file.

Note, the test will call "clone" once. To avoid a runtime error,
make sure that you run this test with "-n2" supplied to the
"config/example/se.py" script.

Change-Id: I505b046b7a4feddfa93a6ef0f0773ac43078cc94
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17112
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/base/
H A Dhostinfo.hhdiff 5202:ff56fa8c2091 Wed Oct 31 21:04:00 EDT 2007 Steve Reinhardt <stever@gmail.com> String constant const-ness changes to placate g++ 4.2.
Also some bug fixes in MIPS ISA uncovered by g++ warnings
(Python string compares don't work in C++!).
diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
H A Dmatch.ccdiff 10231:cb2e6950956d Sat May 31 21:00:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> style: eliminate equality tests with true and false

Using '== true' in a boolean expression is totally redundant,
and using '== false' is pretty verbose (and arguably less
readable in most cases) compared to '!'.

It's somewhat of a pet peeve, perhaps, but I had some time
waiting for some tests to run and decided to clean these up.

Unfortunately, SLICC appears not to have the '!' operator,
so I had to leave the '== false' tests in the SLICC code.
diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
/gem5/src/mem/slicc/ast/
H A DMemberExprAST.pydiff 8644:acf68e5a8cd7 Sat Dec 31 17:38:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> SLICC: Use pointers for directory entries
SLICC uses pointers for cache and TBE entries but not for directory entries.
This patch changes the protocols, SLICC and Ruby memory system so that even
directory entries are referenced using pointers.
diff 8192:be38f7b6ad9e Thu Mar 31 20:18:00 EDT 2011 Lisa Hsu <Lisa.Hsu@amd.com> Ruby: Simplify SLICC and Entry/TBE handling.
Before this changeset, all local variables of type Entry and TBE were considered
to be pointers, but an immediate use of said variables would not be automatically
deferenced in SLICC-generated code. Instead, deferences occurred when such
variables were passed to functions, and were automatically dereferenced in
the bodies of the functions (e.g. the implicitly passed cache_entry).

This is a more general way to do it, which leaves in place the
assumption that parameters to functions and local variables of type AbstractCacheEntry
and TBE are always pointers, but instead of dereferencing to access member variables
on a contextual basis, the dereferencing automatically occurs on a type basis at the
moment a member is being accessed. So, now, things you can do that you couldn't before
include:

Entry foo := getCacheEntry(address);
cache_entry.DataBlk := foo.DataBlk;

or

cache_entry.DataBlk := getCacheEntry(address).DataBlk;

or even

cache_entry.DataBlk := static_cast(Entry, pointer, cache.lookup(address)).DataBlk;
/gem5/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/
H A Dstats.txtdiff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak
diff 10616:6d4da9dc90a1 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> tests: Add a regression for the stack distance calculator

Re-use the existing traffic generator regression, and enable the stack
distance calculation in the comm monitor, along with the verification
stack.

The traffic generator config is also tuned to not increase the
run-time too much (and actually have some address re-use).
/gem5/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/
H A Dstats.txtdiff 11507:be6065c1d8d2 Tue May 31 11:55:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update and fix e273e86a873d
diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak
/gem5/src/arch/x86/
H A Ddecoder_tables.ccdiff 12045:31d9a81ba286 Wed May 24 06:09:00 EDT 2017 Gabe Black <gabeblack@google.com> x86: Rework how VEX prefixes are decoded.

Remove redundant information from the ExtMachInst, hash the vex
information to ensure the decode cache works properly, print the vex info
when printing an ExtMachInst, consider the vex info when comparing two
ExtMachInsts, fold the info from the vex prefixes into existing settings,
remove redundant decode code, handle vex prefixes one byte at a time and
don't bother building up the entire prefix, and let instructions that care
about vex use it in their implementation, instead of developing an entire
parallel decode tree.

This also eliminates the error prone vex immediate decode table which was
incomplete and would result in an out of bounds access for incorrectly
encoded instructions or when the CPU was mispeculating, as it was (as far
as I can tell) redundant with the tables that already existed for two and
three byte opcodes. There were differences, but I think those may have
been mistakes based on the documentation I found.

Also, in 32 bit mode, the VEX prefixes might actually be LDS or LES
instructions which are still legal in that mode. A valid VEX prefix would
look like an LDS/LES with an otherwise invalid modrm encoding, so use that
as a signal to abort processing the VEX and turn the instruction into an
LES/LDS as appropriate.

Change-Id: Icb367eaaa35590692df1c98862f315da4c139f5c
Reviewed-on: https://gem5-review.googlesource.com/3501
Reviewed-by: Joe Gross <joe.gross@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
diff 10924:d02e9c239892 Fri Jul 17 12:31:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> x86: decode instructions with vex prefix

This patch updates the x86 decoder so that it can decode instructions with vex
prefix. It also updates the isa with opcodes from vex opcode maps 1, 2 and 3.
Note that none of the instructions have been implemented yet. The
implementations would be provided in due course of time.
/gem5/src/cpu/
H A Dsmt.hhdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
/gem5/src/dev/
H A Dbaddev.hhdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
H A Drtcreg.hdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
/gem5/src/sim/
H A Dstats.hhdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
/gem5/src/unittest/
H A Dsymtest.ccdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
/gem5/src/arch/mips/
H A Dvtophys.hhdiff 8808:8af87554ad7e Tue Jan 31 00:07:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> Merge with main repository.
/gem5/src/arch/power/
H A Dvtophys.hhdiff 8808:8af87554ad7e Tue Jan 31 00:07:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> Merge with main repository.
/gem5/src/arch/sparc/isa/
H A Dmain.isadiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info

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