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/gem5/src/dev/arm/
H A Dsmmu_v3_caches.ccdiff 14221:2954f631ee64 Tue Aug 20 03:33:00 EDT 2019 Adrian Herrera <adrian.herrera@arm.com> dev-arm: Implement invalidateVA/VAA in SMMUv3 WalkCache

This patch implements VA/VAA invalidations in the SMMUv3 model.

As per SMMUv3.0 spec, if leaf bit is specified in the invalidation
command, only leaf entries within the walk cache need to be invalidated,
otherwise entries with intermediate translations are also invalidated.

Change-Id: I0eb1e1f1d8c00671a3c23d2a8fb756f2020d8d46
Reviewed-by: Michiel van Tol <michiel.vantol@arm.com>
Reviewed-by: Marc Mari Barcelo <marc.maribarcelo@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20258
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A Dsmmu_v3_caches.hhdiff 14221:2954f631ee64 Tue Aug 20 03:33:00 EDT 2019 Adrian Herrera <adrian.herrera@arm.com> dev-arm: Implement invalidateVA/VAA in SMMUv3 WalkCache

This patch implements VA/VAA invalidations in the SMMUv3 model.

As per SMMUv3.0 spec, if leaf bit is specified in the invalidation
command, only leaf entries within the walk cache need to be invalidated,
otherwise entries with intermediate translations are also invalidated.

Change-Id: I0eb1e1f1d8c00671a3c23d2a8fb756f2020d8d46
Reviewed-by: Michiel van Tol <michiel.vantol@arm.com>
Reviewed-by: Marc Mari Barcelo <marc.maribarcelo@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20258
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A Dsmmu_v3.ccdiff 14221:2954f631ee64 Tue Aug 20 03:33:00 EDT 2019 Adrian Herrera <adrian.herrera@arm.com> dev-arm: Implement invalidateVA/VAA in SMMUv3 WalkCache

This patch implements VA/VAA invalidations in the SMMUv3 model.

As per SMMUv3.0 spec, if leaf bit is specified in the invalidation
command, only leaf entries within the walk cache need to be invalidated,
otherwise entries with intermediate translations are also invalidated.

Change-Id: I0eb1e1f1d8c00671a3c23d2a8fb756f2020d8d46
Reviewed-by: Michiel van Tol <michiel.vantol@arm.com>
Reviewed-by: Marc Mari Barcelo <marc.maribarcelo@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20258
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/src/arch/sparc/isa/
H A Doperands.isadiff 2954:6839b9e49575 Sat Jul 22 15:50:00 EDT 2006 Gabe Black <gblack@eecs.umich.edu> Fixed subtract with carry, and started some work with floating point.

src/arch/sparc/isa/decoder.isa:
fixed subc, subccc, added decoding for impdep1 to fit with ua2005, and started work on floating point.
src/arch/sparc/isa/operands.isa:
Added in floating point operands, and changed the numbering of operands.
src/arch/sparc/regfile.hh:
Fixed some memory errors related to floating point.
H A Ddecoder.isadiff 2954:6839b9e49575 Sat Jul 22 15:50:00 EDT 2006 Gabe Black <gblack@eecs.umich.edu> Fixed subtract with carry, and started some work with floating point.

src/arch/sparc/isa/decoder.isa:
fixed subc, subccc, added decoding for impdep1 to fit with ua2005, and started work on floating point.
src/arch/sparc/isa/operands.isa:
Added in floating point operands, and changed the numbering of operands.
src/arch/sparc/regfile.hh:
Fixed some memory errors related to floating point.

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