Searched hist:2906 (Results 1 - 4 of 4) sorted by relevance

/gem5/build_opts/
H A DARMdiff 12068:0097c445aa64 Fri Mar 17 11:11:00 EDT 2017 Nikos Nikoleris <nikos.nikoleris@arm.com> scons: Make MOESI_CMP_directory the default ARM ruby protocol

Previously ARM binaries were by default compiled with the MI_example
protocol. The MI_example protocol cannot properly support load/store
exclusive instructions and therefore it cannot be used to simulate
multicore ARM systems. This change changes to MOESI_CMP_directory as
the default ruby protocol for ARM systems.

Change-Id: I942d950ba466aea9a75f3d8764f9f3eddd0c3baa
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2906
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/testing/
H A Dtests.pydiff 12068:0097c445aa64 Fri Mar 17 11:11:00 EDT 2017 Nikos Nikoleris <nikos.nikoleris@arm.com> scons: Make MOESI_CMP_directory the default ARM ruby protocol

Previously ARM binaries were by default compiled with the MI_example
protocol. The MI_example protocol cannot properly support load/store
exclusive instructions and therefore it cannot be used to simulate
multicore ARM systems. This change changes to MOESI_CMP_directory as
the default ruby protocol for ARM systems.

Change-Id: I942d950ba466aea9a75f3d8764f9f3eddd0c3baa
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2906
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/cpu/o3/
H A Dfetch.hhdiff 2906:3d65b80fdb11 Thu Jul 13 13:09:00 EDT 2006 Kevin Lim <ktlim@umich.edu> Fix for bug when squashing and the fetching. Now fetch checks if the cache data is valid.
H A Dfetch_impl.hhdiff 2906:3d65b80fdb11 Thu Jul 13 13:09:00 EDT 2006 Kevin Lim <ktlim@umich.edu> Fix for bug when squashing and the fetching. Now fetch checks if the cache data is valid.

Completed in 103 milliseconds