Searched hist:2009 (Results 576 - 600 of 951) sorted by relevance

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/gem5/ext/ply/test/
H A Dyacc_error2.pydiff 6498:e21e9ab5fad0 Sun Aug 16 16:39:00 EDT 2009 Nathan Binkert <nate@binkert.org> ply: update PLY to version 3.2
H A Dyacc_error3.pydiff 6498:e21e9ab5fad0 Sun Aug 16 16:39:00 EDT 2009 Nathan Binkert <nate@binkert.org> ply: update PLY to version 3.2
H A Dyacc_inf.pydiff 6498:e21e9ab5fad0 Sun Aug 16 16:39:00 EDT 2009 Nathan Binkert <nate@binkert.org> ply: update PLY to version 3.2
H A Dyacc_missing1.pydiff 6498:e21e9ab5fad0 Sun Aug 16 16:39:00 EDT 2009 Nathan Binkert <nate@binkert.org> ply: update PLY to version 3.2
H A Dyacc_nodoc.pydiff 6498:e21e9ab5fad0 Sun Aug 16 16:39:00 EDT 2009 Nathan Binkert <nate@binkert.org> ply: update PLY to version 3.2
H A Dyacc_noerror.pydiff 6498:e21e9ab5fad0 Sun Aug 16 16:39:00 EDT 2009 Nathan Binkert <nate@binkert.org> ply: update PLY to version 3.2
H A Dyacc_nop.pydiff 6498:e21e9ab5fad0 Sun Aug 16 16:39:00 EDT 2009 Nathan Binkert <nate@binkert.org> ply: update PLY to version 3.2
H A Dyacc_notfunc.pydiff 6498:e21e9ab5fad0 Sun Aug 16 16:39:00 EDT 2009 Nathan Binkert <nate@binkert.org> ply: update PLY to version 3.2
H A Dyacc_notok.pydiff 6498:e21e9ab5fad0 Sun Aug 16 16:39:00 EDT 2009 Nathan Binkert <nate@binkert.org> ply: update PLY to version 3.2
H A Dyacc_rr.pydiff 6498:e21e9ab5fad0 Sun Aug 16 16:39:00 EDT 2009 Nathan Binkert <nate@binkert.org> ply: update PLY to version 3.2
H A Dyacc_simple.pydiff 6498:e21e9ab5fad0 Sun Aug 16 16:39:00 EDT 2009 Nathan Binkert <nate@binkert.org> ply: update PLY to version 3.2
H A Dyacc_sr.pydiff 6498:e21e9ab5fad0 Sun Aug 16 16:39:00 EDT 2009 Nathan Binkert <nate@binkert.org> ply: update PLY to version 3.2
H A Dyacc_term1.pydiff 6498:e21e9ab5fad0 Sun Aug 16 16:39:00 EDT 2009 Nathan Binkert <nate@binkert.org> ply: update PLY to version 3.2
H A Dyacc_unused.pydiff 6498:e21e9ab5fad0 Sun Aug 16 16:39:00 EDT 2009 Nathan Binkert <nate@binkert.org> ply: update PLY to version 3.2
H A Dyacc_uprec.pydiff 6498:e21e9ab5fad0 Sun Aug 16 16:39:00 EDT 2009 Nathan Binkert <nate@binkert.org> ply: update PLY to version 3.2
/gem5/src/arch/mips/isa/
H A Doperands.isadiff 6807:14fbdb0f9585 Thu Dec 31 15:30:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Create an artificial control register to hold the thread pointer.

In Linux, the set_thread_area system call stores the address of the thread
local storage area into a field of the current thread_info structure. Later,
to access that value, the program uses the rdhwr instruction to read a
"hardware register" with index 29. The 64 bit MIPS manual, volume II, says
that index 29 is reserved for a future ABI extension and should cause a
"Reserved Instruction Exception". In Linux (and potentially other ISAs) that
exception is trapped and emulated to return the value stored by
set_thread_area as if that were actually stored by a physical register.

The tp_value address (as named in the Linux kernel) is ironically stored as a
control register so that it goes with a particular ThreadContext. Syscall
emulation will use that to emulate storing to the OS's thread info structure,
and rdhwr will emulate faulting and returning that value from software by
returning the value itself, as if it was in hardware. In other words, we fake
faking the register in SE mode. In an FS mode implementation it should
work as specified in the manual.
diff 6383:31c067ae3331 Wed Jul 22 02:38:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Format the register index constants like the other ISAs.
Also a few more style fixes.
diff 6376:eaf61ef6a8f2 Mon Jul 20 23:14:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Use BitUnions instead of bits() functions and constants.
Also fix style issues in regions around these changes.
diff 6338:14572c7334b5 Fri Jul 10 04:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ISAs: Get rid of the IControl operand type.
A separate operand type is not necessary to use two bitfields to generate the
index.
/gem5/src/arch/x86/isa/microops/
H A Dmicroops.isadiff 6516:b5b420d15a20 Mon Aug 17 21:15:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Set up a media microop framework and create mov2int and mov2fp microops.
/gem5/src/dev/x86/
H A Di8237.hh5818:b47de42ec8b2 Sun Jan 25 23:35:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a dummy minimal DMA controller that doesn't do anything.
H A Dspeaker.hhdiff 5826:e0d0e58cfd8d Sun Feb 01 02:26:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Initialize the value behind port 61 so unused bits are consistent.
H A Dpc.hhdiff 5834:b9e30a60dee4 Sun Feb 01 03:02:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Devices: Add support for legacy fixed IO locations in BARs.
/gem5/src/mem/ruby/network/
H A DSConscript6286:40b142645016 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> scons: update SCons files for changes in ruby.
/gem5/src/mem/slicc/ast/
H A DActionDeclAST.py6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
/gem5/src/arch/mips/
H A Dtypes.hhdiff 6378:4a2ff62c3b4f Tue Jul 21 04:08:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Many style fixes.
White space, commented out code, some other minor fixes.
diff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
diff 6314:781969fbeca9 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Get rid of the float register width parameter.
diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
/gem5/src/dev/mips/
H A Dmalta.hhdiff 6379:75d4aaf7dd54 Tue Jul 21 04:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Get MIPS_FS to compile, more style fixes.
Some breakage was from my BitUnion change, some was much older.
/gem5/src/arch/arm/linux/
H A Dlinux.cc6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5

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