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/gem5/src/arch/riscv/
H A Dmicrocode_rom.hh11723:0596db108c53 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
H A Dmmapped_ipr.hh11723:0596db108c53 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
H A Dpagetable.cc11723:0596db108c53 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
H A Dpra_constants.hh11723:0596db108c53 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
H A Dstacktrace.cc11723:0596db108c53 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
H A Dvtophys.hh11723:0596db108c53 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/arch/x86/insts/
H A Dmicroop.ccdiff 10835:d4b162a57400 Fri May 15 13:39:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Appease gcc 5.1

Three minor issues are resolved:

1. Apparently gcc 5.1 does not like negation of booleans followed by
bitwise AND.

2. Somehow the compiler also gets confused and warns about
NoopMachInst being unused (removing it causes compilation errors
though). Most likely a compiler bug.

3. There seems to be a number of instances where loop unrolling causes
false positives for the array-bounds check. For now, switch to
std::array. Potentially we could disable the warning for newer gcc
versions, but switching to std::array is probably a good move in
any case.
/gem5/src/mem/ruby/profiler/
H A DAccessTraceForAddress.ccdiff 7048:2ab58c54de63 Wed Mar 24 01:49:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: continue style pass
/gem5/tests/configs/
H A Dpc-switcheroo-full.pydiff 11837:17b37f38944a Tue Feb 14 16:09:00 EST 2017 Wendy Elsasser <wendy.elsasser@arm.com> mem: Update DRAM configuration names

Names of DRAM configurations were updated to reflect both
the channel and device data width.

Previous naming format was:
<DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH>

The following nomenclature is now used:
<DEVICE_TYPE>_<DATA_RATE>_<n>x<w>
where n = The number of devices per rank on the channel
x = Device width

Total channel width can be calculated by n*w

Example:
A 64-bit DDR4, 2400 channel consisting of 4-bit devices:
n = 16
w = 4
The resulting configuration name is:
DDR4_2400_16x4

Updated scripts to match new naming convention.

Added unique configurations for DDR4 for:
1) 16x4
2) 8x8
3) 4x16

Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
/gem5/tests/quick/se/00.hello/
H A Dtest.pydiff 8889:2e38fd9937a9 Fri Mar 09 09:59:00 EST 2012 Geoffrey Blake <geoffrey.blake@arm.com> CheckerCPU: Make some basic regression tests for CheckerCPU

Adds regression tests for the CheckerCPU. ARM ISA support
only at this point.
/gem5/src/dev/virtio/
H A DSConscriptdiff 11930:2d22a73fa4c7 Mon Nov 07 13:14:00 EST 2016 Andreas Sandberg <andreas.sandberg@arm.com> dev: Rename VirtIO PCI debug flag

Rename VIOPci -> VIOIface to avoid having a separate flag for the MMIO
interface.

Change-Id: I99f9210fa36ce33662c48537fd3992cd9a69d349
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2324
Reviewed-by: Weiping Liao <weipingliao@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/
H A Dsimerrdiff 11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/
H A Dsimerrdiff 11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/long/se/20.parser/ref/x86/linux/o3-timing/
H A Dsimerrdiff 11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/
H A Dsimerrdiff 11954:19e1cd4edfd2 Thu Mar 30 00:40:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update 01.hello-2T-smt and 40.perlbmks stats on ARM/Alpha o3-timing.

The following change removed a write to an integer register when completing
a system call. This changed the reference statistics slightly.

commit 073cb266079edddec64ea8cd5169dd2cbef8f812
Author: Brandon Potter <brandon.potter@amd.com>
Date: Mon Feb 27 14:10:02 2017 -0500

syscall_emul: [patch 14/22] adds identifier system calls

Change-Id: I3bee42ab826dd9cbc49aab34340da57caf4f045d
Reviewed-on: https://gem5-review.googlesource.com/2650
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/
H A Dsimerrdiff 11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/long/se/70.twolf/ref/arm/linux/o3-timing/
H A Dsimerrdiff 11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/
H A Dsimerrdiff 11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/
H A Dsimerrdiff 11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/
H A Dsimoutdiff 11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/
H A Dsimoutdiff 11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/
H A Dconfig.inidiff 11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/
H A Dconfig.inidiff 11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/
H A Dconfig.inidiff 11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/
H A Dconfig.inidiff 11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

Completed in 61 milliseconds

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