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/gem5/src/arch/x86/isa/insts/x87/stack_management/
H A Dstack_control.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/x87/transcendental_functions/
H A D__init__.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/util/stats/
H A Dflags.py1049:b175a798c8d4 Mon Aug 09 21:20:00 EDT 2004 Nathan Binkert <binkertn@umich.edu> Totally re-do/reorganize the python part of the statistics code
Make the database creation/removal/cleanup code use python
Make formulas work with the database
Add support to do some graphing, but needs more work
Still need to work on vectors, 2d vectors, dists and vectordists
/gem5/src/dev/ps2/
H A Ddevice.hhdiff 12656:335489e574f3 Mon Apr 09 15:07:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> ps2: Unify device data buffering

All PS/2 device currently implement various ad-hoc mechanisms to
handle multi-byte commands. This is error-prone and makes it hard to
implement new devices. Create a buffering mechanism in the base class
to avoid this.

Change-Id: If5638b0ab68decea8de7631ecead0a9ebad1547b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9765
Reviewed-by: Gabe Black <gabeblack@google.com>
12653:4f6b6c1a8e2f Tue Jul 11 11:26:00 EDT 2017 Andreas Sandberg <andreas.sandberg@arm.com> ps2: Factor out PS/2 devices into their own subsystem

PS/2 devices are currently emulated both in the i8042 model and the
Arm KMI model. This is undesirable since it leads to code duplication.

This change introduces a common PS/2 device interface and factor out
the x86 keyboard and mouse model. A subsequent commit will implement
support for this interface in the Arm KMI model.

Change-Id: I440e83517fd9dce362fdc1676db477cc6eee5211
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9762
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
12653:4f6b6c1a8e2f Tue Jul 11 11:26:00 EDT 2017 Andreas Sandberg <andreas.sandberg@arm.com> ps2: Factor out PS/2 devices into their own subsystem

PS/2 devices are currently emulated both in the i8042 model and the
Arm KMI model. This is undesirable since it leads to code duplication.

This change introduces a common PS/2 device interface and factor out
the x86 keyboard and mouse model. A subsequent commit will implement
support for this interface in the Arm KMI model.

Change-Id: I440e83517fd9dce362fdc1676db477cc6eee5211
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9762
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
12653:4f6b6c1a8e2f Tue Jul 11 11:26:00 EDT 2017 Andreas Sandberg <andreas.sandberg@arm.com> ps2: Factor out PS/2 devices into their own subsystem

PS/2 devices are currently emulated both in the i8042 model and the
Arm KMI model. This is undesirable since it leads to code duplication.

This change introduces a common PS/2 device interface and factor out
the x86 keyboard and mouse model. A subsequent commit will implement
support for this interface in the Arm KMI model.

Change-Id: I440e83517fd9dce362fdc1676db477cc6eee5211
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9762
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/
H A Dendian_conversion.pydiff 6478:2ec6bfc8f9c7 Fri Aug 07 13:12:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the qaud width bswap instruction handle the fact that 32 bit operations zero extend.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/
H A Dconditional_move.pydiff 6473:2b1bb253c05e Fri Aug 07 00:44:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix a copy/paste error for cmovnp.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/integer/data_conversion/
H A Dconvert_gpr_integer_to_floating_point.pydiff 6563:2c5b80c75da7 Mon Aug 17 21:41:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the media instructions that convert integer values to floating point.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/base/
H A Dbarrier.hh9983:2cce74fe359e Mon Nov 25 12:21:00 EST 2013 Steve Reinhardt <stever@gmail.com>, Nilay Vaish <nilay@cs.wisc.edu>, Ali Saidi <Ali.Saidi@ARM.com> sim: simulate with multiple threads and event queues
This patch adds support for simulating with multiple threads, each of
which operates on an event queue. Each sim object specifies which eventq
is would like to be on. A custom barrier implementation is being added
using which eventqs synchronize.

The patch was tested in two different configurations:
1. ruby_network_test.py: in this simulation L1 cache controllers receive
requests from the cpu. The requests are replied to immediately without
any communication taking place with any other level.
2. twosys-tsunami-simple-atomic: this configuration simulates a client-server
system which are connected by an ethernet link.

We still lack the ability to communicate using message buffers or ports. But
other things like simulation start and end, synchronizing after every quantum
are working.

Committed by: Nilay Vaish
9983:2cce74fe359e Mon Nov 25 12:21:00 EST 2013 Steve Reinhardt <stever@gmail.com>, Nilay Vaish <nilay@cs.wisc.edu>, Ali Saidi <Ali.Saidi@ARM.com> sim: simulate with multiple threads and event queues
This patch adds support for simulating with multiple threads, each of
which operates on an event queue. Each sim object specifies which eventq
is would like to be on. A custom barrier implementation is being added
using which eventqs synchronize.

The patch was tested in two different configurations:
1. ruby_network_test.py: in this simulation L1 cache controllers receive
requests from the cpu. The requests are replied to immediately without
any communication taking place with any other level.
2. twosys-tsunami-simple-atomic: this configuration simulates a client-server
system which are connected by an ethernet link.

We still lack the ability to communicate using message buffers or ports. But
other things like simulation start and end, synchronizing after every quantum
are working.

Committed by: Nilay Vaish
/gem5/util/cpt_upgraders/
H A Detherswitch.pydiff 11776:ed89cb178ecd Mon Dec 19 01:12:00 EST 2016 Curtis Dunham <Curtis.Dunham@arm.com> dist, dev: fix etherswitch upgrade script

The aforementioned upgrader in [1] assumes every option in [system]
has a delimiting '.', and also seems to do its rewriting work a bit too
unconditionally. Most checkpoints in the wild don't have this device,
in which case this script should be a safe no-op.

[1] 2aa4d7b dist, dev: Fixed the packet ordering in etherswitch

Change-Id: Icfd0350985109df1628eb9ab864cda42c54060a8
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
11533:2aa4d7bd47ec Wed Jun 08 10:12:00 EDT 2016 Mohammad Alian <m.alian1369@gmail.com> dist, dev: Fixed the packet ordering in etherswitch

This patch fixes the order that packets gets pushed into the output fifo
of etherswitch. If two packets arrive at the same tick to the etherswitch,
we sort and push them based on their source port id.
In dist-gem5 simulations, if there is no ordering inforced while two
packets arrive at the same tick, it can lead to non-deterministic simulations

Committed by Jason Lowe-Power <power.jg@gmail.com>
/gem5/src/dev/x86/
H A Dsouth_bridge.ccdiff 6216:2f4020838149 Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: sort includes again
diff 5643:2b1611137af4 Sat Oct 11 19:08:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create an IO APIC device.
H A Dsouth_bridge.hhdiff 5643:2b1611137af4 Sat Oct 11 19:08:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create an IO APIC device.
/gem5/configs/boot/
H A Dbbench-gb.rcS9070:fa77985a87c6 Mon Jun 11 11:07:00 EDT 2012 Anthony Gutierrez <atgutier@umich.edu> configs: add run scripts for ics/gb versions of android and bbench

1) Modifies Benchmarks.py to add support for Android ICS and BBench on Android ICS.

2) An rcS script is added for BBench on ICS.

3) Separates benchmark entries and rcS scripts for GB/ICS

4) Removes the debugging output from the existing BBench run script. These
print statements were used for debugging and they seemed to confuse users
into believing they should see some terminal output.
H A Dbbench-ics.rcS9070:fa77985a87c6 Mon Jun 11 11:07:00 EDT 2012 Anthony Gutierrez <atgutier@umich.edu> configs: add run scripts for ics/gb versions of android and bbench

1) Modifies Benchmarks.py to add support for Android ICS and BBench on Android ICS.

2) An rcS script is added for BBench on ICS.

3) Separates benchmark entries and rcS scripts for GB/ICS

4) Removes the debugging output from the existing BBench run script. These
print statements were used for debugging and they seemed to confuse users
into believing they should see some terminal output.
/gem5/src/arch/x86/isa/insts/general_purpose/
H A D__init__.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dno_operation.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/
H A Dtest.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/
H A Dconditional_jump.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/
H A Dconvert_floating_point_to_mmx_integer.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dconvert_floating_point_to_xmm_integer.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_reordering/
H A Dshuffle.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/
H A Dmove_mask.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dmove_with_duplication.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/floating_point/logical/
H A Dorp.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/integer/arithmetic/
H A Daverage.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dsum_of_absolute_differences.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.

Completed in 42 milliseconds

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