Searched hist:13996 (Results 1 - 9 of 9) sorted by relevance
| /gem5/src/dev/arm/ | ||
| H A D | gic_v3.hh | diff 13996:8a567118e670 Tue Apr 16 04:20:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Provide a GICv3 ITS Implementation This patch introduces the GICv3 ITS module, which is in charge of translating MSIs into physical (GICv3) and virtual (GICv4) LPIs. The patch is only GICv3 compliant, which means that there is no direct virtual LPI injection (this also means V* commands are unimplemented) Other missing features are: * No 2level ITS tables (only flat table supported) * Command errors: when there is an error in the ITS, it is IMPLEMENTATION DEFINED on how the ITS behaves. There are three possible scenarios (see GICv3 TRM) and this implementation only supports one of these (which is, aborting the command and jumping to the next one). Furter patches could make it possible to select different reactions * Invalidation commands (INV, INVALL) are only doing the memory table walks, assuming the current Gicv3Redistributor is not caching any configuration table entry. Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18601 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | gic_v3_its.hh | 13996:8a567118e670 Tue Apr 16 04:20:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Provide a GICv3 ITS Implementation This patch introduces the GICv3 ITS module, which is in charge of translating MSIs into physical (GICv3) and virtual (GICv4) LPIs. The patch is only GICv3 compliant, which means that there is no direct virtual LPI injection (this also means V* commands are unimplemented) Other missing features are: * No 2level ITS tables (only flat table supported) * Command errors: when there is an error in the ITS, it is IMPLEMENTATION DEFINED on how the ITS behaves. There are three possible scenarios (see GICv3 TRM) and this implementation only supports one of these (which is, aborting the command and jumping to the next one). Furter patches could make it possible to select different reactions * Invalidation commands (INV, INVALL) are only doing the memory table walks, assuming the current Gicv3Redistributor is not caching any configuration table entry. Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18601 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | gic_v3.cc | diff 13996:8a567118e670 Tue Apr 16 04:20:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Provide a GICv3 ITS Implementation This patch introduces the GICv3 ITS module, which is in charge of translating MSIs into physical (GICv3) and virtual (GICv4) LPIs. The patch is only GICv3 compliant, which means that there is no direct virtual LPI injection (this also means V* commands are unimplemented) Other missing features are: * No 2level ITS tables (only flat table supported) * Command errors: when there is an error in the ITS, it is IMPLEMENTATION DEFINED on how the ITS behaves. There are three possible scenarios (see GICv3 TRM) and this implementation only supports one of these (which is, aborting the command and jumping to the next one). Furter patches could make it possible to select different reactions * Invalidation commands (INV, INVALL) are only doing the memory table walks, assuming the current Gicv3Redistributor is not caching any configuration table entry. Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18601 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | gic_v3_its.cc | 13996:8a567118e670 Tue Apr 16 04:20:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Provide a GICv3 ITS Implementation This patch introduces the GICv3 ITS module, which is in charge of translating MSIs into physical (GICv3) and virtual (GICv4) LPIs. The patch is only GICv3 compliant, which means that there is no direct virtual LPI injection (this also means V* commands are unimplemented) Other missing features are: * No 2level ITS tables (only flat table supported) * Command errors: when there is an error in the ITS, it is IMPLEMENTATION DEFINED on how the ITS behaves. There are three possible scenarios (see GICv3 TRM) and this implementation only supports one of these (which is, aborting the command and jumping to the next one). Furter patches could make it possible to select different reactions * Invalidation commands (INV, INVALL) are only doing the memory table walks, assuming the current Gicv3Redistributor is not caching any configuration table entry. Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18601 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | gic_v3_redistributor.hh | diff 13996:8a567118e670 Tue Apr 16 04:20:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Provide a GICv3 ITS Implementation This patch introduces the GICv3 ITS module, which is in charge of translating MSIs into physical (GICv3) and virtual (GICv4) LPIs. The patch is only GICv3 compliant, which means that there is no direct virtual LPI injection (this also means V* commands are unimplemented) Other missing features are: * No 2level ITS tables (only flat table supported) * Command errors: when there is an error in the ITS, it is IMPLEMENTATION DEFINED on how the ITS behaves. There are three possible scenarios (see GICv3 TRM) and this implementation only supports one of these (which is, aborting the command and jumping to the next one). Furter patches could make it possible to select different reactions * Invalidation commands (INV, INVALL) are only doing the memory table walks, assuming the current Gicv3Redistributor is not caching any configuration table entry. Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18601 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | Gic.py | diff 13996:8a567118e670 Tue Apr 16 04:20:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Provide a GICv3 ITS Implementation This patch introduces the GICv3 ITS module, which is in charge of translating MSIs into physical (GICv3) and virtual (GICv4) LPIs. The patch is only GICv3 compliant, which means that there is no direct virtual LPI injection (this also means V* commands are unimplemented) Other missing features are: * No 2level ITS tables (only flat table supported) * Command errors: when there is an error in the ITS, it is IMPLEMENTATION DEFINED on how the ITS behaves. There are three possible scenarios (see GICv3 TRM) and this implementation only supports one of these (which is, aborting the command and jumping to the next one). Furter patches could make it possible to select different reactions * Invalidation commands (INV, INVALL) are only doing the memory table walks, assuming the current Gicv3Redistributor is not caching any configuration table entry. Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18601 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | SConscript | diff 13996:8a567118e670 Tue Apr 16 04:20:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Provide a GICv3 ITS Implementation This patch introduces the GICv3 ITS module, which is in charge of translating MSIs into physical (GICv3) and virtual (GICv4) LPIs. The patch is only GICv3 compliant, which means that there is no direct virtual LPI injection (this also means V* commands are unimplemented) Other missing features are: * No 2level ITS tables (only flat table supported) * Command errors: when there is an error in the ITS, it is IMPLEMENTATION DEFINED on how the ITS behaves. There are three possible scenarios (see GICv3 TRM) and this implementation only supports one of these (which is, aborting the command and jumping to the next one). Furter patches could make it possible to select different reactions * Invalidation commands (INV, INVALL) are only doing the memory table walks, assuming the current Gicv3Redistributor is not caching any configuration table entry. Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18601 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | RealView.py | diff 13996:8a567118e670 Tue Apr 16 04:20:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Provide a GICv3 ITS Implementation This patch introduces the GICv3 ITS module, which is in charge of translating MSIs into physical (GICv3) and virtual (GICv4) LPIs. The patch is only GICv3 compliant, which means that there is no direct virtual LPI injection (this also means V* commands are unimplemented) Other missing features are: * No 2level ITS tables (only flat table supported) * Command errors: when there is an error in the ITS, it is IMPLEMENTATION DEFINED on how the ITS behaves. There are three possible scenarios (see GICv3 TRM) and this implementation only supports one of these (which is, aborting the command and jumping to the next one). Furter patches could make it possible to select different reactions * Invalidation commands (INV, INVALL) are only doing the memory table walks, assuming the current Gicv3Redistributor is not caching any configuration table entry. Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18601 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| /gem5/src/arch/arm/ | ||
| H A D | miscregs.hh | diff 13392:a292af6523cc Wed Oct 31 10:24:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Remove MISCREG commented numbers Having an enum number might be useful in case we wanted to know how many miscregs we have, but on the other hand it makes it tedious to update the register list, since every commented number must be bumped. This patch is removing the comments holding the MISCREG numbers Change-Id: Ic5aba93885e4b8d6cb3bd6a4c49900b9e5474276 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13996 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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