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| /gem5/src/arch/arm/insts/ | ||
| H A D | static_inst.hh | diff 13369:c130351b4278 Mon Oct 29 08:44:00 EDT 2018 Yuetsu Kodama <yuetsu.kodama@riken.jp> arch-arm: FIXUP for the add PRFM PST instruction commit Change-Id: I898e5b565c6591f88ae732b24713aeae2c827cbd Reviewed-on: https://gem5-review.googlesource.com/c/13815 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/arm/isa/ | ||
| H A D | operands.isa | diff 13815:be0ad772ae61 Tue Mar 26 14:02:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix index generation for VecElem operands Current operand generation is not providing VecElems with the right vector index and element index. The bug was covered when registers were 128 bit wide, but with SVE we have augmented the vector register size and the bug has been exposed. E.g. With dest = 2, FpDestP2 = (vec_index = 0, elem_index = 4) whereas it should be FpDestP2 = (vec_index = 1, elem_index = 0) Change-Id: Iad02fb477afd0d3dd3d437bf2ca4338fbd142107 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17710 |
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