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| H A D | operands.isa | diff 13603:203e36327db9 Mon Dec 17 04:27:00 EST 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Use VecElem instead of FloatReg for FP instruction SIMD & FP Operations use FloatRegs in AArch32 mode and VecRegs in AArch64 mode. The usage of two different register pools breaks interprocessing between A32 and A64. This patch is changing definition of arm operands so that they are backed by VecElems in A32, which are mapped to the same storage as A64 VecRegs. Change-Id: I54e2ea0ef1ae61d29aca57ab09acb589d82c1217 Reviewed-on: https://gem5-review.googlesource.com/c/15603 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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