Searched hist:13517 (Results 1 - 5 of 5) sorted by relevance
/gem5/src/systemc/ext/ | ||
H A D | tlm | diff 13517:64279791af98 Tue Dec 11 02:16:00 EST 2018 Gabe Black <gabeblack@google.com> systemc: Include cstring in the tlm header file. A lot of TLM implementation assumes the string functions (memcpy, memset, etc) are available, but don't include cstring. Lets do that for them to avoid having to fix up a lot of places. Change-Id: I1f26d3a227fe2cefc2613e24cbb0333216e46ee9 Reviewed-on: https://gem5-review.googlesource.com/c/15060 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> |
/gem5/src/cpu/o3/ | ||
H A D | O3CPU.py | diff 13710:5ba1d8066ef0 Mon Jun 25 11:59:00 EDT 2018 Gabor Dozsa <gabor.dozsa@arm.com> cpu-o3: Add cache read ports limit to LSQ This change introduces cache read ports to limit the number of per-cycle loads. Previously only the number of per-cycle stores could be limited. Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13517 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | lsq.hh | diff 13710:5ba1d8066ef0 Mon Jun 25 11:59:00 EDT 2018 Gabor Dozsa <gabor.dozsa@arm.com> cpu-o3: Add cache read ports limit to LSQ This change introduces cache read ports to limit the number of per-cycle loads. Previously only the number of per-cycle stores could be limited. Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13517 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | lsq_impl.hh | diff 13710:5ba1d8066ef0 Mon Jun 25 11:59:00 EDT 2018 Gabor Dozsa <gabor.dozsa@arm.com> cpu-o3: Add cache read ports limit to LSQ This change introduces cache read ports to limit the number of per-cycle loads. Previously only the number of per-cycle stores could be limited. Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13517 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | lsq_unit_impl.hh | diff 13710:5ba1d8066ef0 Mon Jun 25 11:59:00 EDT 2018 Gabor Dozsa <gabor.dozsa@arm.com> cpu-o3: Add cache read ports limit to LSQ This change introduces cache read ports to limit the number of per-cycle loads. Previously only the number of per-cycle stores could be limited. Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13517 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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