Searched hist:13104 (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/arch/generic/ | ||
| H A D | vec_reg.hh | diff 13119:398a93017471 Tue Nov 07 09:05:00 EST 2017 Gabor Dozsa <gabor.dozsa@arm.com> arch: Fix unserialization of VectorReg value Change-Id: Iba01ae60e10703877eae299ba924fa1f04a4a387 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13104 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/arm/ | ||
| H A D | pmu.hh | diff 13104:4a0713e11ef7 Tue Sep 04 07:17:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: raise/clear IRQ when writing to PMOVSCLR/SET Writing a 1 to the Overflow Flag Status register should trigger an interrupt raise/clear depending on the register we are currently using (PMOVSCLR for clearing and PMOVSSET for raising). Change-Id: I2091456685a245712045cf7a4932ac36b7dded1d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12531 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | pmu.cc | diff 13104:4a0713e11ef7 Tue Sep 04 07:17:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: raise/clear IRQ when writing to PMOVSCLR/SET Writing a 1 to the Overflow Flag Status register should trigger an interrupt raise/clear depending on the register we are currently using (PMOVSCLR for clearing and PMOVSSET for raising). Change-Id: I2091456685a245712045cf7a4932ac36b7dded1d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12531 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
Completed in 21 milliseconds