Searched hist:12673 (Results 1 - 1 of 1) sorted by relevance
/gem5/src/arch/arm/isa/formats/ | ||
H A D | aarch64.isa | diff 12673:b862f22eeed9 Wed Apr 18 05:31:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Change disassemble when MSR to UNKNOWN register This patch changes the fault being thrown when MSR/MRS to an unknown Misc register in AArch64. While previously the instruction was decoded as an Unknown instruction (hence not printing any information), it is now decoded as a FailUnimplemented and the unrecognized System register numbers (CRn, op0...) are printed. Change-Id: I205ff7adcde5934231c77e8d2250db69a34581fc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10061 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
Completed in 11 milliseconds