Searched hist:12639 (Results 1 - 1 of 1) sorted by relevance
| /gem5/src/arch/arm/ | ||
| H A D | isa.cc | diff 12639:c133e5b397a4 Tue Mar 27 11:22:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix secure write of SCTLR when EL3 is AArch64 MiscRegisters are not banked between secure and non-secure mode if EL3 is not implemented or if EL3 is using AArch64 (highestELIs64). In this scenario a unique register is used and it is mapped to the NS version (see snsBankedIndex implementation), so that a secure world read/write should access the non secure storage. Change-Id: Ica4182e3cdf4021d2bd1db23e477ce2bbf055926 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9502 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
Completed in 31 milliseconds