Searched hist:12323 (Results 1 - 5 of 5) sorted by relevance
| /gem5/src/arch/riscv/insts/ | ||
| H A D | amo.hh | 12323:55d08b81ff39 Fri Nov 10 00:23:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Remove static parts of AMOs out of ISA This patch removes the static parts of the RISC-V atomic memory instructions out of the ISA generated code and into arch/riscv/insts. It also makes the LR and SC instructions subclasses of MemInst from arch/riscv/insts/mem.hh. Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51 Reviewed-on: https://gem5-review.googlesource.com/6025 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
| H A D | amo.cc | 12323:55d08b81ff39 Fri Nov 10 00:23:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Remove static parts of AMOs out of ISA This patch removes the static parts of the RISC-V atomic memory instructions out of the ISA generated code and into arch/riscv/insts. It also makes the LR and SC instructions subclasses of MemInst from arch/riscv/insts/mem.hh. Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51 Reviewed-on: https://gem5-review.googlesource.com/6025 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
| H A D | SConscript | diff 12323:55d08b81ff39 Fri Nov 10 00:23:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Remove static parts of AMOs out of ISA This patch removes the static parts of the RISC-V atomic memory instructions out of the ISA generated code and into arch/riscv/insts. It also makes the LR and SC instructions subclasses of MemInst from arch/riscv/insts/mem.hh. Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51 Reviewed-on: https://gem5-review.googlesource.com/6025 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
| /gem5/src/arch/riscv/isa/ | ||
| H A D | includes.isa | diff 12323:55d08b81ff39 Fri Nov 10 00:23:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Remove static parts of AMOs out of ISA This patch removes the static parts of the RISC-V atomic memory instructions out of the ISA generated code and into arch/riscv/insts. It also makes the LR and SC instructions subclasses of MemInst from arch/riscv/insts/mem.hh. Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51 Reviewed-on: https://gem5-review.googlesource.com/6025 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
| /gem5/src/arch/riscv/isa/formats/ | ||
| H A D | amo.isa | diff 12323:55d08b81ff39 Fri Nov 10 00:23:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Remove static parts of AMOs out of ISA This patch removes the static parts of the RISC-V atomic memory instructions out of the ISA generated code and into arch/riscv/insts. It also makes the LR and SC instructions subclasses of MemInst from arch/riscv/insts/mem.hh. Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51 Reviewed-on: https://gem5-review.googlesource.com/6025 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
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