Searched hist:10210 (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/mem/ | ||
| H A D | DRAMCtrl.py | diff 10210:793e5ff26e0b Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add tWR to DRAM activate and precharge constraints This patch adds the write recovery time to the DRAM timing constraints, and changes the current tRASDoneAt to a more generic preAllowedAt, capturing when a precharge is allowed to take place. The part of the DRAM access code that accounts for the precharge and activate constraints is updated accordingly. |
| H A D | dram_ctrl.hh | diff 10210:793e5ff26e0b Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add tWR to DRAM activate and precharge constraints This patch adds the write recovery time to the DRAM timing constraints, and changes the current tRASDoneAt to a more generic preAllowedAt, capturing when a precharge is allowed to take place. The part of the DRAM access code that accounts for the precharge and activate constraints is updated accordingly. |
| H A D | dram_ctrl.cc | diff 10210:793e5ff26e0b Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add tWR to DRAM activate and precharge constraints This patch adds the write recovery time to the DRAM timing constraints, and changes the current tRASDoneAt to a more generic preAllowedAt, capturing when a precharge is allowed to take place. The part of the DRAM access code that accounts for the precharge and activate constraints is updated accordingly. |
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