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| /gem5/src/arch/x86/ | ||
| H A D | faults.cc | diff 10100:24cfe67c0749 Mon Mar 03 08:44:00 EST 2014 Andreas Sandberg <andreas@sandberg.pp.se> x86: Setup correct TSL/TR segment attributes on INIT The TSL/LDT & TR/TSS segments didn't contain valid attributes. This caused problems when transfering the state into KVM where invalid state is a no-go. Fixup the attributes with values from AMD's architecture programmer's manual. |
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