Searched hist:10025 (Results 1 - 7 of 7) sorted by relevance
| /gem5/src/dev/serial/ | ||
| H A D | simple.cc | 12689:f554325372e9 Mon Feb 26 12:27:00 EST 2018 Andreas Sandberg <andreas.sandberg@arm.com> dev: Add support for a simple debug UART Add a simple memory-mapped device that forwards writes to a serial devices and treats reads as reads from the device. Unlike real UART models, this one doesn't support interrupts. This is useful to implement various debug devices that exist in many systems. Change-Id: I1e4300e4d3b70825a15d03f47d4e026941f9066c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10025 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
| H A D | simple.hh | 12689:f554325372e9 Mon Feb 26 12:27:00 EST 2018 Andreas Sandberg <andreas.sandberg@arm.com> dev: Add support for a simple debug UART Add a simple memory-mapped device that forwards writes to a serial devices and treats reads as reads from the device. Unlike real UART models, this one doesn't support interrupts. This is useful to implement various debug devices that exist in many systems. Change-Id: I1e4300e4d3b70825a15d03f47d4e026941f9066c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10025 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
| H A D | SConscript | diff 12689:f554325372e9 Mon Feb 26 12:27:00 EST 2018 Andreas Sandberg <andreas.sandberg@arm.com> dev: Add support for a simple debug UART Add a simple memory-mapped device that forwards writes to a serial devices and treats reads as reads from the device. Unlike real UART models, this one doesn't support interrupts. This is useful to implement various debug devices that exist in many systems. Change-Id: I1e4300e4d3b70825a15d03f47d4e026941f9066c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10025 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
| H A D | Uart.py | diff 12689:f554325372e9 Mon Feb 26 12:27:00 EST 2018 Andreas Sandberg <andreas.sandberg@arm.com> dev: Add support for a simple debug UART Add a simple memory-mapped device that forwards writes to a serial devices and treats reads as reads from the device. Unlike real UART models, this one doesn't support interrupts. This is useful to implement various debug devices that exist in many systems. Change-Id: I1e4300e4d3b70825a15d03f47d4e026941f9066c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10025 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
| /gem5/src/mem/cache/tags/ | ||
| H A D | Tags.py | diff 10025:fdf737112e46 Fri Jan 24 16:29:00 EST 2014 Timothy M. Jones <timothy.jones@arm.com> Cache: Collect very basic stats on tag and data accesses Adds very basic statistics on the number of tag and data accesses within the cache, which is important for power modelling. For the tags, simply count the associativity of the cache each time. For the data, this depends on whether tags and data are accessed sequentially, which is given by a new parameter. In the parallel case, all data blocks are accessed each time, but with sequential accesses, a single data block is accessed only on a hit. |
| H A D | base.cc | diff 10025:fdf737112e46 Fri Jan 24 16:29:00 EST 2014 Timothy M. Jones <timothy.jones@arm.com> Cache: Collect very basic stats on tag and data accesses Adds very basic statistics on the number of tag and data accesses within the cache, which is important for power modelling. For the tags, simply count the associativity of the cache each time. For the data, this depends on whether tags and data are accessed sequentially, which is given by a new parameter. In the parallel case, all data blocks are accessed each time, but with sequential accesses, a single data block is accessed only on a hit. |
| H A D | base.hh | diff 10025:fdf737112e46 Fri Jan 24 16:29:00 EST 2014 Timothy M. Jones <timothy.jones@arm.com> Cache: Collect very basic stats on tag and data accesses Adds very basic statistics on the number of tag and data accesses within the cache, which is important for power modelling. For the tags, simply count the associativity of the cache each time. For the data, this depends on whether tags and data are accessed sequentially, which is given by a new parameter. In the parallel case, all data blocks are accessed each time, but with sequential accesses, a single data block is accessed only on a hit. |
Completed in 42 milliseconds