Searched defs:tCCD_L (Results 1 - 2 of 2) sorted by relevance

/gem5/src/mem/
H A DDRAMCtrl.py190 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay") variable in class:DRAMCtrl
586 tCCD_L = '5ns'; variable in class:DDR4_2400_16x4
1029 tCCD_L = '3ns'; variable in class:GDDR5_4000_2x32
H A Ddram_ctrl.hh992 const Tick tCCD_L; member in class:DRAMCtrl

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