Searched defs:sequential_access (Results 1 - 3 of 3) sorted by relevance

/gem5/src/mem/cache/tags/
H A DTags.py65 sequential_access = Param.Bool(Parent.sequential_access, variable in class:BaseTags
/gem5/configs/dram/
H A Dlat_mem_rd.py272 sequential_access = True variable in class:L3Cache
/gem5/src/mem/cache/
H A DCache.py110 sequential_access = Param.Bool(False, variable in class:BaseCache

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