| /gem5/src/arch/arm/ |
| H A D | stage2_lookup.cc | 82 Stage2LookUp::mergeTe(const RequestPtr &req, BaseTLB::Mode mode) argument
179 Stage2LookUp::finish(const Fault &_fault, const RequestPtr &req, argument
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| H A D | vtophys.cc | 73 auto req = std::make_shared<Request>(0, addr, 64, 0x40, -1, 0, 0); local
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| H A D | locked_mem.hh | 94 handleLockedRead(XC *xc, const RequestPtr &req) argument
114 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
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| H A D | stage2_mmu.cc | 70 auto req = std::make_shared<Request>(); local
120 finish(const Fault &_fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) argument
[all...] |
| H A D | stage2_mmu.hh | 75 RequestPtr req; member in class:ArmISA::Stage2MMU::Stage2Translation
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| /gem5/ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_adapters/ |
| H A D | tlm_adapters.h | 88 REQ req; local
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| /gem5/src/arch/alpha/ |
| H A D | locked_mem.hh | 88 handleLockedRead(XC *xc, const RequestPtr &req) argument
102 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
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| /gem5/src/arch/generic/ |
| H A D | locked_mem.hh | 66 handleLockedRead(XC *xc, const RequestPtr &req) argument
79 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
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| H A D | tlb.cc | 40 GenericTLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode) argument
55 GenericTLB::translateTiming(const RequestPtr &req, ThreadContext *tc, argument
59 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); local
63 GenericTLB::finalizePhysical(const RequestPtr &req, ThreadContext *tc, argument
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| H A D | tlb.hh | 98 translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode) argument
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| /gem5/src/arch/mips/ |
| H A D | locked_mem.hh | 78 handleLockedRead(XC *xc, const RequestPtr &req) argument
95 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
[all...] |
| /gem5/src/cpu/testers/directedtest/ |
| H A D | SeriesRequestGenerator.cc | 63 RequestPtr req = std::make_shared<Request>(m_address, 1, flags, masterId); local
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| H A D | InvalidateGenerator.cc | 63 RequestPtr req = std::make_shared<Request>(m_address, 1, flags, masterId); local
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| /gem5/src/arch/riscv/ |
| H A D | locked_mem.hh | 88 handleLockedRead(XC *xc, const RequestPtr &req) argument
102 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
[all...] |
| /gem5/src/systemc/ext/tlm_core/1/req_rsp/adapters/ |
| H A D | adapters.hh | 50 transport(const REQ &req) argument
87 REQ req; local
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| /gem5/src/mem/ |
| H A D | port_proxy.cc | 51 auto req = std::make_shared<Request>( local
68 auto req = std::make_shared<Request>( local
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| H A D | page_table.cc | 157 EmulationPageTable::translate(const RequestPtr &req) argument
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| /gem5/ext/sst/ |
| H A D | ExtSlave.cc | 178 RequestPtr req = std::make_shared<Request>( local
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| H A D | ExtMaster.cc | 174 auto req = std::make_shared<Request>(ev->getAddr(), ev->getSize(), flags, 0); local
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| /gem5/src/dev/virtio/ |
| H A D | block.cc | 71 VirtIOBlock::read(const BlkRequest &req, VirtDescriptor *desc_chain, argument
97 VirtIOBlock::write(const BlkRequest &req, VirtDescriptor *desc_chain, argument
133 BlkRequest req; local
[all...] |
| /gem5/src/cpu/testers/traffic_gen/ |
| H A D | base_gen.cc | 65 RequestPtr req = std::make_shared<Request>(addr, size, flags, masterID); local
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| /gem5/src/dev/arm/ |
| H A D | rv_ctrl.cc | 166 CfgCtrlReg req = pkt->getLE<uint32_t>(); local
[all...] |
| /gem5/src/gpu-compute/ |
| H A D | fetch_unit.cc | 148 RequestPtr req = std::make_shared<Request>( local
[all...] |
| /gem5/src/systemc/ext/tlm_core/1/req_rsp/channels/req_rsp_channels/ |
| H A D | put_get_imp.hh | 97 tlm_master_imp(tlm_put_if<REQ> &req, tlm_get_peek_if<RSP> &rsp) : argument
107 tlm_slave_imp(tlm_get_peek_if<REQ> &req, tlm_put_if<RSP> &rsp) : argument
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| /gem5/src/systemc/ext/tlm_core/1/req_rsp/interfaces/ |
| H A D | core_ifs.hh | 36 transport(const REQ &req, RSP &rsp) argument
|