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| /gem5/src/systemc/tests/systemc/misc/sim_tests/cycle_dw8051_demo/ |
| H A D | cycle_model.h | 187 cycle_model(sc_module_name NAME, const sc_signal_in_if<bool>& CLK, char* hex_file_name, signal_bool_vector16& MEM_ADDR, signal_bool_vector8& MEM_DATA_OUT, const signal_bool_vector8& MEM_DATA_IN, sc_signal<bool>& MEM_WR_N, sc_signal<bool>& MEM_RD_N, sc_signal<bool>& MEM_PSWR_N, sc_signal<bool>& MEM_PSRD_N, sc_signal<bool>& MEM_ALE, const sc_signal<bool>& MEM_EA_N, sc_signal<bool>& P0_MEM_REG_N, sc_signal<bool>& P0_ADDR_DATA_N, sc_signal<bool>& P2_MEM_REG_N ) argument
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