---------- Begin Simulation Statistics ---------- sim_seconds 1.203606 # Number of seconds simulated sim_ticks 1203606499000 # Number of ticks simulated final_tick 1203606499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 418240 # Simulator instruction rate (inst/s) host_op_rate 532998 # Simulator op (including micro ops) rate (op/s) host_tick_rate 8191230777 # Simulator tick rate (ticks/s) host_mem_usage 386340 # Number of bytes of host memory used host_seconds 146.94 # Real time elapsed on the host sim_insts 61455549 # Number of instructions simulated sim_ops 78317886 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 354084 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 364956 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 5307824 # Number of bytes read from this memory system.physmem.bytes_read::total 62191076 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 354084 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 364956 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4163904 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory system.physmem.bytes_written::total 7191248 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 11751 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 66623 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 5784 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 82961 # Number of read requests responded to by this memory system.physmem.num_reads::total 6655190 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 65061 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory system.physmem.num_writes::total 821897 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 43124154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 294186 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 3538741 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 303219 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 4409933 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 51670605 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 294186 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 303219 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 597405 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 3459523 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 14124 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 2501103 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 5974750 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 3459523 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 43124154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 294186 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 3552865 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 303219 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 6911036 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 57645355 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 70188 # number of replacements system.l2c.tagsinuse 53228.072476 # Cycle average of tags in use system.l2c.total_refs 1643838 # Total number of references to valid blocks. system.l2c.sampled_refs 135351 # Sample count of references to valid blocks. system.l2c.avg_refs 12.145001 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.occ_blocks::writebacks 40453.574010 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000402 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.003089 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.inst 3394.604865 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.data 2735.402876 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.dtb.walker 2.669960 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.inst 3118.943835 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.data 3522.873439 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.617273 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.051798 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.041739 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.047591 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.053755 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.812196 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 2523 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1490 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 278308 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 124645 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 5210 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 1502 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 576222 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 223363 # number of ReadReq hits system.l2c.ReadReq_hits::total 1213263 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 571562 # number of Writeback hits system.l2c.Writeback_hits::total 571562 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 992 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 878 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 1870 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 189 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 96 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 285 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 39231 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 70244 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 109475 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 2523 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 1490 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 278308 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 163876 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 5210 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 1502 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 576222 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 293607 # number of demand (read+write) hits system.l2c.demand_hits::total 1322738 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 2523 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 1490 # number of overall hits system.l2c.overall_hits::cpu0.inst 278308 # number of overall hits system.l2c.overall_hits::cpu0.data 163876 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 5210 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 1502 # number of overall hits system.l2c.overall_hits::cpu1.inst 576222 # number of overall hits system.l2c.overall_hits::cpu1.data 293607 # number of overall hits system.l2c.overall_hits::total 1322738 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 5119 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 6000 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 5697 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 5608 # number of ReadReq misses system.l2c.ReadReq_misses::total 22431 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 4011 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 4908 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 8919 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 652 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 388 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1040 # number of SCUpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 61450 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 78839 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 140289 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 5119 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 67450 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 5697 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 84447 # number of demand (read+write) misses system.l2c.demand_misses::total 162720 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses system.l2c.overall_misses::cpu0.inst 5119 # number of overall misses system.l2c.overall_misses::cpu0.data 67450 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses system.l2c.overall_misses::cpu1.inst 5697 # number of overall misses system.l2c.overall_misses::cpu1.data 84447 # number of overall misses system.l2c.overall_misses::total 162720 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 156500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.inst 267825000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 313081000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 156000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.inst 298083000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 292866500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 1172220000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.data 15780999 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 31202500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 46983499 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1357500 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6172500 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 7530000 # number of SCUpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 3221673990 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 4120152496 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 7341826486 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 156500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.inst 267825000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 3534754990 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 156000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 298083000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 4413018996 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 8514046486 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 156500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 267825000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 3534754990 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 156000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 298083000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 4413018996 # number of overall miss cycles system.l2c.overall_miss_latency::total 8514046486 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 2524 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 1493 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 283427 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 130645 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 5213 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 1502 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 581919 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 228971 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1235694 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 571562 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 571562 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 5003 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 5786 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 10789 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 841 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 484 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1325 # number of SCUpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 100681 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 149083 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 249764 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 2524 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 1493 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 283427 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 231326 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 5213 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 1502 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 581919 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 378054 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1485458 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 2524 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 1493 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 283427 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 231326 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 5213 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 1502 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 581919 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 378054 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1485458 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.002009 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.018061 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.045926 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000575 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.009790 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.024492 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.018153 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.801719 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.848254 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.826675 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.775268 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.801653 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.784906 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.610344 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.528826 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.561686 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.002009 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.018061 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.291580 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000575 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.009790 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.223373 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.109542 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.002009 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.018061 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.291580 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000575 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.009790 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.223373 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.109542 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52166.666667 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52319.789021 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52180.166667 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52322.801474 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 52222.985021 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 52258.927377 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3934.430067 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6357.477588 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 5267.798968 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2082.055215 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15908.505155 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 7240.384615 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52427.566965 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52260.334302 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 52333.586283 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52166.666667 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52319.789021 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52405.559526 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 52322.801474 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 52257.853991 # average overall miss latency system.l2c.demand_avg_miss_latency::total 52323.294530 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52166.666667 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52319.789021 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52405.559526 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 52322.801474 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 52257.853991 # average overall miss latency system.l2c.overall_avg_miss_latency::total 52323.294530 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 65061 # number of writebacks system.l2c.writebacks::total 65061 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.inst 5118 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.data 6000 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.inst 5697 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 5608 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 22430 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 4011 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 4908 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 8919 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 652 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 388 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 1040 # number of SCUpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 61450 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 78839 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 140289 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 5118 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 67450 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 5697 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 84447 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 5118 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 67450 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 5697 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 84447 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 162719 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 120000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 204790500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.data 240017000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 120000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 227965500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 224340500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 897393500 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 160489997 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 196385999 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 356875996 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 26081499 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15523499 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 41604998 # number of SCUpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2458644990 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3153935496 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 5612580486 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 120000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 204790500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 2698661990 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 120000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 227965500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 3378275996 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 6509973986 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 120000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 204790500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 2698661990 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 120000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 227965500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 3378275996 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 6509973986 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11136863000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155607031000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 167013375500 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1070738498 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30849143000 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 31919881498 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12207601498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.data 186456174000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 198933256998 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.045926 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024492 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.018152 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801719 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.848254 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.826675 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.775268 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.801653 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784906 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.610344 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.528826 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.561686 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.291580 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.223373 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.109541 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.291580 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.223373 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.109541 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40002.833333 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40003.655492 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 40008.626839 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40012.464971 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40013.447229 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40013.005494 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40002.299080 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40009.018041 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40004.805769 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40010.496176 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40004.762820 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 40007.274170 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40009.814529 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40004.689284 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 40007.460628 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40009.814529 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40004.689284 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 40007.460628 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 4800569 # DTB read hits system.cpu0.dtb.read_misses 2116 # DTB read misses system.cpu0.dtb.write_hits 4101188 # DTB write hits system.cpu0.dtb.write_misses 405 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1539 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions system.cpu0.dtb.read_accesses 4802685 # DTB read accesses system.cpu0.dtb.write_accesses 4101593 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses system.cpu0.dtb.hits 8901757 # DTB hits system.cpu0.dtb.misses 2521 # DTB misses system.cpu0.dtb.accesses 8904278 # DTB accesses system.cpu0.itb.inst_hits 19425317 # ITB inst hits system.cpu0.itb.inst_misses 1350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.inst_accesses 19426667 # ITB inst accesses system.cpu0.itb.hits 19425317 # DTB hits system.cpu0.itb.misses 1350 # DTB misses system.cpu0.itb.accesses 19426667 # DTB accesses system.cpu0.numCycles 2405785466 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 19048205 # Number of instructions committed system.cpu0.committedOps 25051835 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 22684157 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses system.cpu0.num_func_calls 868672 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 2620308 # number of instructions that are conditional controls system.cpu0.num_int_insts 22684157 # number of integer instructions system.cpu0.num_fp_insts 4364 # number of float instructions system.cpu0.num_int_register_reads 128951400 # number of times the integer registers were read system.cpu0.num_int_register_writes 23731440 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written system.cpu0.num_mem_refs 9388218 # number of memory refs system.cpu0.num_load_insts 5047895 # Number of load instructions system.cpu0.num_store_insts 4340323 # Number of store instructions system.cpu0.num_idle_cycles 2301327262.807119 # Number of idle cycles system.cpu0.num_busy_cycles 104458203.192881 # Number of busy cycles system.cpu0.not_idle_fraction 0.043420 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.956580 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 34019 # number of quiesce instructions executed system.cpu0.icache.replacements 283204 # number of replacements system.cpu0.icache.tagsinuse 509.502445 # Cycle average of tags in use system.cpu0.icache.total_refs 19141584 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 283716 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 67.467411 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 75588601000 # Cycle when the warmup percentage was hit. system.cpu0.icache.occ_blocks::cpu0.inst 509.502445 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.995122 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.995122 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 19141584 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 19141584 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 19141584 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 19141584 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 19141584 # number of overall hits system.cpu0.icache.overall_hits::total 19141584 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 283716 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 283716 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 283716 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 283716 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 283716 # number of overall misses system.cpu0.icache.overall_misses::total 283716 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3929859500 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::total 3929859500 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu0.inst 3929859500 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::total 3929859500 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu0.inst 3929859500 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 3929859500 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 19425300 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 19425300 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 19425300 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 19425300 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 19425300 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 19425300 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014605 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.014605 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014605 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.014605 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014605 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.014605 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13851.384836 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total 13851.384836 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13851.384836 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total 13851.384836 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13851.384836 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total 13851.384836 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 283716 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 283716 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 283716 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 283716 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 283716 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 283716 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 3362427500 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 3362427500 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 3362427500 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::total 3362427500 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 3362427500 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 3362427500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 353907000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 353907000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 353907000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 353907000 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014605 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.014605 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.014605 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11851.384836 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 11851.384836 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 11851.384836 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 220249 # number of replacements system.cpu0.dcache.tagsinuse 456.517669 # Cycle average of tags in use system.cpu0.dcache.total_refs 8560161 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 220619 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 38.800652 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 656029000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.occ_blocks::cpu0.data 456.517669 # Average occupied blocks per requestor system.cpu0.dcache.occ_percent::cpu0.data 0.891636 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.891636 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 4452439 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 4452439 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 3852551 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 3852551 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117730 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 117730 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 117854 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 117854 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.data 8304990 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 8304990 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 8304990 # number of overall hits system.cpu0.dcache.overall_hits::total 8304990 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 146457 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 146457 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 116961 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 116961 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7881 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 7881 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7692 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 7692 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 263418 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 263418 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 263418 # number of overall misses system.cpu0.dcache.overall_misses::total 263418 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 1991139500 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 1991139500 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4199443500 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 4199443500 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 70259000 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 70259000 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 66131000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 66131000 # number of StoreCondReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu0.data 6190583000 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 6190583000 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu0.data 6190583000 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 6190583000 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 4598896 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 4598896 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 3969512 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 3969512 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125611 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 125611 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125546 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 125546 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 8568408 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 8568408 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 8568408 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 8568408 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031846 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.031846 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.029465 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.029465 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062741 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062741 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061268 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061268 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030743 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.030743 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030743 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.030743 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13595.386359 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 13595.386359 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35904.647703 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 35904.647703 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 8914.985408 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8914.985408 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8597.373895 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8597.373895 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23500.987024 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 23500.987024 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23500.987024 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 23500.987024 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 205058 # number of writebacks system.cpu0.dcache.writebacks::total 205058 # number of writebacks system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146457 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 146457 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116961 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 116961 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7881 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7881 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7690 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 7690 # number of StoreCondReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 263418 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 263418 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 263418 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 263418 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698225500 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698225500 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965521500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965521500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54497000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54497000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50753000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50753000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5663747000 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 5663747000 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5663747000 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 5663747000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130745000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130745000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193494500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193494500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324239500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324239500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031846 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031846 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029465 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029465 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062741 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062741 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061252 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061252 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11595.386359 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11595.386359 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33904.647703 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33904.647703 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6914.985408 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6914.985408 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6599.869961 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6599.869961 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 10589201 # DTB read hits system.cpu1.dtb.read_misses 5231 # DTB read misses system.cpu1.dtb.write_hits 7383574 # DTB write hits system.cpu1.dtb.write_misses 1834 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 193 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions system.cpu1.dtb.read_accesses 10594432 # DTB read accesses system.cpu1.dtb.write_accesses 7385408 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses system.cpu1.dtb.hits 17972775 # DTB hits system.cpu1.dtb.misses 7065 # DTB misses system.cpu1.dtb.accesses 17979840 # DTB accesses system.cpu1.itb.inst_hits 43338256 # ITB inst hits system.cpu1.itb.inst_misses 3017 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.inst_accesses 43341273 # ITB inst accesses system.cpu1.itb.hits 43338256 # DTB hits system.cpu1.itb.misses 3017 # DTB misses system.cpu1.itb.accesses 43341273 # DTB accesses system.cpu1.numCycles 2407212998 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 42407344 # Number of instructions committed system.cpu1.committedOps 53266051 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 47734651 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses system.cpu1.num_func_calls 1334953 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 5482869 # number of instructions that are conditional controls system.cpu1.num_int_insts 47734651 # number of integer instructions system.cpu1.num_fp_insts 5457 # number of float instructions system.cpu1.num_int_register_reads 274813771 # number of times the integer registers were read system.cpu1.num_int_register_writes 51971016 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written system.cpu1.num_mem_refs 18681443 # number of memory refs system.cpu1.num_load_insts 10999206 # Number of load instructions system.cpu1.num_store_insts 7682237 # Number of store instructions system.cpu1.num_idle_cycles 1827286039.250482 # Number of idle cycles system.cpu1.num_busy_cycles 579926958.749518 # Number of busy cycles system.cpu1.not_idle_fraction 0.240912 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.759088 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 56704 # number of quiesce instructions executed system.cpu1.icache.replacements 582576 # number of replacements system.cpu1.icache.tagsinuse 479.066528 # Cycle average of tags in use system.cpu1.icache.total_refs 42755164 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 583088 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 73.325405 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 92849627500 # Cycle when the warmup percentage was hit. system.cpu1.icache.occ_blocks::cpu1.inst 479.066528 # Average occupied blocks per requestor system.cpu1.icache.occ_percent::cpu1.inst 0.935677 # Average percentage of cache occupancy system.cpu1.icache.occ_percent::total 0.935677 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 42755164 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 42755164 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 42755164 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 42755164 # number of demand (read+write) hits system.cpu1.icache.overall_hits::cpu1.inst 42755164 # number of overall hits system.cpu1.icache.overall_hits::total 42755164 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 583088 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 583088 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 583088 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 583088 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 583088 # number of overall misses system.cpu1.icache.overall_misses::total 583088 # number of overall misses system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7852005500 # number of ReadReq miss cycles system.cpu1.icache.ReadReq_miss_latency::total 7852005500 # number of ReadReq miss cycles system.cpu1.icache.demand_miss_latency::cpu1.inst 7852005500 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_latency::total 7852005500 # number of demand (read+write) miss cycles system.cpu1.icache.overall_miss_latency::cpu1.inst 7852005500 # number of overall miss cycles system.cpu1.icache.overall_miss_latency::total 7852005500 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 43338252 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 43338252 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 43338252 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 43338252 # number of demand (read+write) accesses system.cpu1.icache.overall_accesses::cpu1.inst 43338252 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 43338252 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013454 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.013454 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013454 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.013454 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013454 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.013454 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13466.244375 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total 13466.244375 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13466.244375 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total 13466.244375 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13466.244375 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total 13466.244375 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 583088 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 583088 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 583088 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 583088 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 583088 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 583088 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6685829500 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_latency::total 6685829500 # number of ReadReq MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6685829500 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::total 6685829500 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6685829500 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 6685829500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5251000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5251000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5251000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 5251000 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013454 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.013454 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.013454 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average ReadReq mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11466.244375 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average overall mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::total 11466.244375 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 11466.244375 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 401285 # number of replacements system.cpu1.dcache.tagsinuse 473.299929 # Cycle average of tags in use system.cpu1.dcache.total_refs 15679399 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 401797 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 39.023186 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 84382221000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.occ_blocks::cpu1.data 473.299929 # Average occupied blocks per requestor system.cpu1.dcache.occ_percent::cpu1.data 0.924414 # Average percentage of cache occupancy system.cpu1.dcache.occ_percent::total 0.924414 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 9100620 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 9100620 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 6322619 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 6322619 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 111839 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 111839 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 114463 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 114463 # number of StoreCondReq hits system.cpu1.dcache.demand_hits::cpu1.data 15423239 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 15423239 # number of demand (read+write) hits system.cpu1.dcache.overall_hits::cpu1.data 15423239 # number of overall hits system.cpu1.dcache.overall_hits::total 15423239 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 253127 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 253127 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 178055 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 178055 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13099 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 13099 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10399 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 10399 # number of StoreCondReq misses system.cpu1.dcache.demand_misses::cpu1.data 431182 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 431182 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 431182 # number of overall misses system.cpu1.dcache.overall_misses::total 431182 # number of overall misses system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3277248500 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 3277248500 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5648876500 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 5648876500 # number of WriteReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 115793500 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::total 115793500 # number of LoadLockedReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 63008000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 63008000 # number of StoreCondReq miss cycles system.cpu1.dcache.demand_miss_latency::cpu1.data 8926125000 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_latency::total 8926125000 # number of demand (read+write) miss cycles system.cpu1.dcache.overall_miss_latency::cpu1.data 8926125000 # number of overall miss cycles system.cpu1.dcache.overall_miss_latency::total 8926125000 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 9353747 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 9353747 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 6500674 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 6500674 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 124938 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 124938 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 124862 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 124862 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.demand_accesses::cpu1.data 15854421 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 15854421 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 15854421 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 15854421 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027062 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.027062 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027390 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.027390 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104844 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104844 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083284 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083284 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027196 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.027196 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027196 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.027196 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12947.052270 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 12947.052270 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31725.458426 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 31725.458426 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8839.873273 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8839.873273 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6059.044139 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6059.044139 # average StoreCondReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20701.525110 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 20701.525110 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20701.525110 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 20701.525110 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 366504 # number of writebacks system.cpu1.dcache.writebacks::total 366504 # number of writebacks system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253127 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 253127 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178055 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 178055 # number of WriteReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13099 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13099 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10394 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 10394 # number of StoreCondReq MSHR misses system.cpu1.dcache.demand_mshr_misses::cpu1.data 431182 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 431182 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 431182 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 431182 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2770994500 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2770994500 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5292766500 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5292766500 # number of WriteReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89595500 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89595500 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42224000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42224000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8063761000 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::total 8063761000 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8063761000 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 8063761000 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170066366500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170066366500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40314514000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40314514000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210380880500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210380880500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027062 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027390 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027390 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104844 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104844 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083244 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083244 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.027196 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.027196 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.052270 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.052270 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29725.458426 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29725.458426 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6839.873273 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6839.873273 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4062.343660 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4062.343660 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.avg_refs nan # Average number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 522347967555 # number of ReadReq MSHR uncacheable cycles system.iocache.ReadReq_mshr_uncacheable_latency::total 522347967555 # number of ReadReq MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::realview.clcd 522347967555 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 522347967555 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ----------