---------- Begin Simulation Statistics ---------- sim_seconds 5.163317 # Number of seconds simulated sim_ticks 5163317092500 # Number of ticks simulated final_tick 5163317092500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 184798 # Simulator instruction rate (inst/s) host_op_rate 364169 # Simulator op (including micro ops) rate (op/s) host_tick_rate 2236864416 # Simulator tick rate (ticks/s) host_mem_usage 361200 # Number of bytes of host memory used host_seconds 2308.28 # Real time elapsed on the host sim_insts 426565585 # Number of instructions simulated sim_ops 840604148 # Number of ops (including micro ops) simulated system.physmem.bytes_read 15861056 # Number of bytes read from this memory system.physmem.bytes_inst_read 1233408 # Number of instructions bytes read from this memory system.physmem.bytes_written 12134976 # Number of bytes written to this memory system.physmem.num_reads 247829 # Number of read requests responded to by this memory system.physmem.num_writes 189609 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory system.physmem.bw_read 3071873 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read 238879 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write 2350229 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total 5422102 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 168510 # number of replacements system.l2c.tagsinuse 37865.450237 # Cycle average of tags in use system.l2c.total_refs 3777661 # Total number of references to valid blocks. system.l2c.sampled_refs 200841 # Sample count of references to valid blocks. system.l2c.avg_refs 18.809212 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.occ_blocks::writebacks 26765.864627 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.dtb.walker 11.948564 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.itb.walker 0.042262 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.inst 2364.419048 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.data 8723.175736 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.408415 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.dtb.walker 0.000182 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.inst 0.036078 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.data 0.133105 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.577781 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu.dtb.walker 134155 # number of ReadReq hits system.l2c.ReadReq_hits::cpu.itb.walker 7302 # number of ReadReq hits system.l2c.ReadReq_hits::cpu.inst 1001370 # number of ReadReq hits system.l2c.ReadReq_hits::cpu.data 1325429 # number of ReadReq hits system.l2c.ReadReq_hits::total 2468256 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1603120 # number of Writeback hits system.l2c.Writeback_hits::total 1603120 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 322 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 322 # number of UpgradeReq hits system.l2c.ReadExReq_hits::cpu.data 150704 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 150704 # number of ReadExReq hits system.l2c.demand_hits::cpu.dtb.walker 134155 # number of demand (read+write) hits system.l2c.demand_hits::cpu.itb.walker 7302 # number of demand (read+write) hits system.l2c.demand_hits::cpu.inst 1001370 # number of demand (read+write) hits system.l2c.demand_hits::cpu.data 1476133 # number of demand (read+write) hits system.l2c.demand_hits::total 2618960 # number of demand (read+write) hits system.l2c.overall_hits::cpu.dtb.walker 134155 # number of overall hits system.l2c.overall_hits::cpu.itb.walker 7302 # number of overall hits system.l2c.overall_hits::cpu.inst 1001370 # number of overall hits system.l2c.overall_hits::cpu.data 1476133 # number of overall hits system.l2c.overall_hits::total 2618960 # number of overall hits system.l2c.ReadReq_misses::cpu.dtb.walker 82 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 10 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.inst 19273 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.data 44950 # number of ReadReq misses system.l2c.ReadReq_misses::total 64315 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu.data 5079 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 5079 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu.data 141389 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 141389 # number of ReadExReq misses system.l2c.demand_misses::cpu.dtb.walker 82 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 10 # number of demand (read+write) misses system.l2c.demand_misses::cpu.inst 19273 # number of demand (read+write) misses system.l2c.demand_misses::cpu.data 186339 # number of demand (read+write) misses system.l2c.demand_misses::total 205704 # number of demand (read+write) misses system.l2c.overall_misses::cpu.dtb.walker 82 # number of overall misses system.l2c.overall_misses::cpu.itb.walker 10 # number of overall misses system.l2c.overall_misses::cpu.inst 19273 # number of overall misses system.l2c.overall_misses::cpu.data 186339 # number of overall misses system.l2c.overall_misses::total 205704 # number of overall misses system.l2c.ReadReq_miss_latency::cpu.dtb.walker 4278000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu.itb.walker 521000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu.inst 1007154000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu.data 2362722500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 3374675500 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu.data 37477500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 37477500 # number of UpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu.data 7363267000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 7363267000 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu.dtb.walker 4278000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu.itb.walker 521000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu.inst 1007154000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu.data 9725989500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 10737942500 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu.dtb.walker 4278000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu.itb.walker 521000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu.inst 1007154000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu.data 9725989500 # number of overall miss cycles system.l2c.overall_miss_latency::total 10737942500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu.dtb.walker 134237 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu.itb.walker 7312 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu.inst 1020643 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu.data 1370379 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2532571 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 1603120 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1603120 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu.data 5401 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 5401 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu.data 292093 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 292093 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu.dtb.walker 134237 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu.itb.walker 7312 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu.inst 1020643 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu.data 1662472 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2824664 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu.dtb.walker 134237 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu.itb.walker 7312 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu.inst 1020643 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu.data 1662472 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2824664 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000611 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001368 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.018883 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.032801 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.940381 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.484055 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.000611 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.001368 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.018883 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.112085 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.000611 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.001368 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.018883 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.112085 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52170.731707 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52100 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.inst 52257.251077 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52563.348165 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 7378.913172 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52078.075381 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52170.731707 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 52100 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52257.251077 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52195.136284 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52170.731707 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 52100 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52257.251077 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52195.136284 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 142942 # number of writebacks system.l2c.writebacks::total 142942 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 82 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu.itb.walker 10 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu.inst 19272 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu.data 44949 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 64313 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu.data 5079 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 5079 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu.data 141389 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 141389 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu.dtb.walker 82 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu.itb.walker 10 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu.inst 19272 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu.data 186338 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 205702 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu.dtb.walker 82 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu.itb.walker 10 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu.inst 19272 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu.data 186338 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 205702 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 3286000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 400000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu.inst 771698500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu.data 1813525000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 2588909500 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 203533000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 203533000 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5656832000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 5656832000 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 3286000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu.itb.walker 400000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu.inst 771698500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu.data 7470357000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 8245741500 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 3286000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu.itb.walker 400000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu.inst 771698500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu.data 7470357000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 8245741500 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59975483500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 59975483500 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1228994000 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 1228994000 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu.data 61204477500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 61204477500 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000611 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001368 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.018882 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.032800 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.940381 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.484055 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000611 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001368 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.018882 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.112085 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000611 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001368 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.018882 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.112085 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40073.170732 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40042.470942 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40346.281341 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40073.439653 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40008.996457 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40073.170732 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40042.470942 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.357308 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40073.170732 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40042.470942 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.357308 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47580 # number of replacements system.iocache.tagsinuse 0.183883 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 47596 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 4996389534000 # Cycle when the warmup percentage was hit. system.iocache.occ_blocks::pc.south_bridge.ide 0.183883 # Average occupied blocks per requestor system.iocache.occ_percent::pc.south_bridge.ide 0.011493 # Average percentage of cache occupancy system.iocache.occ_percent::total 0.011493 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 915 # number of ReadReq misses system.iocache.ReadReq_misses::total 915 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses system.iocache.demand_misses::pc.south_bridge.ide 47635 # number of demand (read+write) misses system.iocache.demand_misses::total 47635 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47635 # number of overall misses system.iocache.overall_misses::total 47635 # number of overall misses system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 114575932 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 114575932 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6365614160 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 6365614160 # number of WriteReq miss cycles system.iocache.demand_miss_latency::pc.south_bridge.ide 6480190092 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 6480190092 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::pc.south_bridge.ide 6480190092 # number of overall miss cycles system.iocache.overall_miss_latency::total 6480190092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 915 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::pc.south_bridge.ide 47635 # number of demand (read+write) accesses system.iocache.demand_accesses::total 47635 # number of demand (read+write) accesses system.iocache.overall_accesses::pc.south_bridge.ide 47635 # number of overall (read+write) accesses system.iocache.overall_accesses::total 47635 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125219.597814 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136250.303082 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136038.419062 # average overall miss latency system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136038.419062 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 68485452 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 11259 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 6082.729550 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 915 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 915 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses system.iocache.demand_mshr_misses::pc.south_bridge.ide 47635 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 47635 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47635 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47635 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66972982 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 66972982 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3935855798 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 3935855798 # number of WriteReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4002828780 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 4002828780 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4002828780 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 4002828780 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73194.515847 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84243.488827 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84031.253910 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84031.253910 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. system.cpu.numCycles 462460674 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 91001984 # Number of BP lookups system.cpu.BPredUnit.condPredicted 91001984 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 1246670 # Number of conditional branches incorrect system.cpu.BPredUnit.BTBLookups 89740974 # Number of BTB lookups system.cpu.BPredUnit.BTBHits 83587498 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 28956413 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 449639850 # Number of instructions fetch has processed system.cpu.fetch.Branches 91001984 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 83587498 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 171222727 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 5870168 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 127753 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.BlockedCycles 101915873 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 36574 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 38952 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 241 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 9672092 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 512695 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 3312 # Number of outstanding ITLB misses that were squashed system.cpu.fetch.rateDist::samples 306883426 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.884320 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.377751 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 136151197 44.37% 44.37% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 1833476 0.60% 44.96% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 72801112 23.72% 68.69% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 1413943 0.46% 69.15% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 1812929 0.59% 69.74% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 3984448 1.30% 71.04% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 1563806 0.51% 71.55% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 1664583 0.54% 72.09% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 85657932 27.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 306883426 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.196778 # Number of branch fetches per cycle system.cpu.fetch.rate 0.972277 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 34101035 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 98103338 # Number of cycles decode is blocked system.cpu.decode.RunCycles 165554285 # Number of cycles decode is running system.cpu.decode.UnblockCycles 4539875 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 4584893 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 881320225 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 609 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 4584893 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 38485909 # Number of cycles rename is idle system.cpu.rename.BlockCycles 67729275 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 11421097 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 165177226 # Number of cycles rename is running system.cpu.rename.UnblockCycles 19485026 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 876989303 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 10814 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 12483638 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 3869558 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 878639289 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 1719877661 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 1719877141 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 520 # Number of floating rename lookups system.cpu.rename.CommittedMaps 843209199 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 35430083 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 491480 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 496551 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 46051608 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 19446241 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 10506071 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1193626 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 915732 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 869497074 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 1725725 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 866404799 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 123854 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 29753009 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 42786279 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 206033 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 306883426 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.823238 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.403588 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 100067522 32.61% 32.61% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 25349299 8.26% 40.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 13936726 4.54% 45.41% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 9650933 3.14% 48.55% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 79503599 25.91% 74.46% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 4853866 1.58% 76.04% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 72832557 23.73% 99.78% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 561211 0.18% 99.96% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 127713 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 306883426 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 188296 8.84% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.84% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 1773429 83.29% 92.13% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 167520 7.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 304337 0.04% 0.04% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 831186392 95.94% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.97% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 25424398 2.93% 98.90% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 9489672 1.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 866404799 # Type of FU issued system.cpu.iq.rate 1.873467 # Inst issue rate system.cpu.iq.fu_busy_cnt 2129245 # FU busy when requested system.cpu.iq.fu_busy_rate 0.002458 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 2042097119 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 900986111 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 855761606 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 229 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 242 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 868229599 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 108 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 1634850 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 4122229 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 17231 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 11383 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 2082513 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7821289 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 4333 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 4584893 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 45441721 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 6142722 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 871222799 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 285751 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 19446241 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 10506071 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 891740 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 5368443 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 12385 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 11383 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 896223 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 525625 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1421848 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 864338156 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 24982156 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 2066642 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 34234409 # number of memory reference insts executed system.cpu.iew.exec_branches 86668621 # Number of branches executed system.cpu.iew.exec_stores 9252253 # Number of stores executed system.cpu.iew.exec_rate 1.868998 # Inst execution rate system.cpu.iew.wb_sent 863811947 # cumulative count of insts sent to commit system.cpu.iew.wb_count 855761668 # cumulative count of insts written-back system.cpu.iew.wb_producers 670084242 # num instructions producing a value system.cpu.iew.wb_consumers 1169301773 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.850453 # insts written-back per cycle system.cpu.iew.wb_fanout 0.573064 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 426565585 # The number of committed instructions system.cpu.commit.commitCommittedOps 840604148 # The number of committed instructions system.cpu.commit.commitSquashedInsts 30510484 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1519690 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1250933 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 302314482 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.780562 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.862970 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 121547491 40.21% 40.21% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 14447999 4.78% 44.98% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 4300765 1.42% 46.41% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 76650469 25.35% 71.76% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 3947228 1.31% 73.07% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 1803648 0.60% 73.66% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 1077125 0.36% 74.02% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 71984746 23.81% 97.83% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 6555011 2.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 302314482 # Number of insts commited each cycle system.cpu.commit.committedInsts 426565585 # Number of instructions committed system.cpu.commit.committedOps 840604148 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 23747567 # Number of memory references committed system.cpu.commit.loads 15324009 # Number of loads committed system.cpu.commit.membars 781567 # Number of memory barriers committed system.cpu.commit.branches 85515141 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 768433298 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 6555011 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.rob.rob_reads 1166791668 # The number of ROB reads system.cpu.rob.rob_writes 1746826364 # The number of ROB writes system.cpu.timesIdled 2858532 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 155577248 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.quiesceCycles 9864170951 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.committedInsts 426565585 # Number of Instructions Simulated system.cpu.committedOps 840604148 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 426565585 # Number of Instructions Simulated system.cpu.cpi 1.084149 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.084149 # CPI: Total CPI of All Threads system.cpu.ipc 0.922382 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.922382 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 1406313694 # number of integer regfile reads system.cpu.int_regfile_writes 857070459 # number of integer regfile writes system.cpu.fp_regfile_reads 62 # number of floating regfile reads system.cpu.misc_regfile_reads 281985005 # number of misc regfile reads system.cpu.misc_regfile_writes 409504 # number of misc regfile writes system.cpu.icache.replacements 1020153 # number of replacements system.cpu.icache.tagsinuse 509.928344 # Cycle average of tags in use system.cpu.icache.total_refs 8587640 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1020665 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 8.413769 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 56648796000 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 509.928344 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.995954 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.995954 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 8587640 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 8587640 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 8587640 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 8587640 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 8587640 # number of overall hits system.cpu.icache.overall_hits::total 8587640 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1084449 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1084449 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1084449 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1084449 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1084449 # number of overall misses system.cpu.icache.overall_misses::total 1084449 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 16282601991 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 16282601991 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 16282601991 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 16282601991 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 16282601991 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 16282601991 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 9672089 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 9672089 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 9672089 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 9672089 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 9672089 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 9672089 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.112121 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.112121 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.112121 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15014.631385 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 15014.631385 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 15014.631385 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 2694492 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 263 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 10245.216730 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 1551 # number of writebacks system.cpu.icache.writebacks::total 1551 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60108 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 60108 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 60108 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 60108 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 60108 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 60108 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1024341 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 1024341 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 1024341 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 1024341 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1024341 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1024341 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12392610492 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 12392610492 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12392610492 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 12392610492 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12392610492 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12392610492 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.105907 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.105907 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.105907 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12098.129912 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12098.129912 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12098.129912 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 8553 # number of replacements system.cpu.itb_walker_cache.tagsinuse 6.010935 # Cycle average of tags in use system.cpu.itb_walker_cache.total_refs 26637 # Total number of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 8564 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 3.110346 # Average number of references to valid blocks. system.cpu.itb_walker_cache.warmup_cycle 5140402124000 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.010935 # Average occupied blocks per requestor system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375683 # Average percentage of cache occupancy system.cpu.itb_walker_cache.occ_percent::total 0.375683 # Average percentage of cache occupancy system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26742 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 26742 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26745 # number of demand (read+write) hits system.cpu.itb_walker_cache.demand_hits::total 26745 # number of demand (read+write) hits system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26745 # number of overall hits system.cpu.itb_walker_cache.overall_hits::total 26745 # number of overall hits system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9424 # number of ReadReq misses system.cpu.itb_walker_cache.ReadReq_misses::total 9424 # number of ReadReq misses system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9424 # number of demand (read+write) misses system.cpu.itb_walker_cache.demand_misses::total 9424 # number of demand (read+write) misses system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9424 # number of overall misses system.cpu.itb_walker_cache.overall_misses::total 9424 # number of overall misses system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 120935500 # number of ReadReq miss cycles system.cpu.itb_walker_cache.ReadReq_miss_latency::total 120935500 # number of ReadReq miss cycles system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 120935500 # number of demand (read+write) miss cycles system.cpu.itb_walker_cache.demand_miss_latency::total 120935500 # number of demand (read+write) miss cycles system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 120935500 # number of overall miss cycles system.cpu.itb_walker_cache.overall_miss_latency::total 120935500 # number of overall miss cycles system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36166 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.ReadReq_accesses::total 36166 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36169 # number of demand (read+write) accesses system.cpu.itb_walker_cache.demand_accesses::total 36169 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36169 # number of overall (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::total 36169 # number of overall (read+write) accesses system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.260576 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.260555 # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.260555 # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12832.714346 # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12832.714346 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12832.714346 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed system.cpu.itb_walker_cache.writebacks::writebacks 1616 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 1616 # number of writebacks system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9424 # number of ReadReq MSHR misses system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9424 # number of ReadReq MSHR misses system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9424 # number of demand (read+write) MSHR misses system.cpu.itb_walker_cache.demand_mshr_misses::total 9424 # number of demand (read+write) MSHR misses system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9424 # number of overall MSHR misses system.cpu.itb_walker_cache.overall_mshr_misses::total 9424 # number of overall MSHR misses system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 92324000 # number of ReadReq MSHR miss cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 92324000 # number of ReadReq MSHR miss cycles system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 92324000 # number of demand (read+write) MSHR miss cycles system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 92324000 # number of demand (read+write) MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 92324000 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 92324000 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.260576 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.260555 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.260555 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9796.689304 # average ReadReq mshr miss latency system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9796.689304 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9796.689304 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.replacements 140574 # number of replacements system.cpu.dtb_walker_cache.tagsinuse 13.858803 # Cycle average of tags in use system.cpu.dtb_walker_cache.total_refs 148049 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.sampled_refs 140589 # Sample count of references to valid blocks. system.cpu.dtb_walker_cache.avg_refs 1.053062 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.warmup_cycle 5108661869000 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.858803 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.866175 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.occ_percent::total 0.866175 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 148058 # number of ReadReq hits system.cpu.dtb_walker_cache.ReadReq_hits::total 148058 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 148058 # number of demand (read+write) hits system.cpu.dtb_walker_cache.demand_hits::total 148058 # number of demand (read+write) hits system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 148058 # number of overall hits system.cpu.dtb_walker_cache.overall_hits::total 148058 # number of overall hits system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 141571 # number of ReadReq misses system.cpu.dtb_walker_cache.ReadReq_misses::total 141571 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 141571 # number of demand (read+write) misses system.cpu.dtb_walker_cache.demand_misses::total 141571 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 141571 # number of overall misses system.cpu.dtb_walker_cache.overall_misses::total 141571 # number of overall misses system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1989434500 # number of ReadReq miss cycles system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1989434500 # number of ReadReq miss cycles system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1989434500 # number of demand (read+write) miss cycles system.cpu.dtb_walker_cache.demand_miss_latency::total 1989434500 # number of demand (read+write) miss cycles system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1989434500 # number of overall miss cycles system.cpu.dtb_walker_cache.overall_miss_latency::total 1989434500 # number of overall miss cycles system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 289629 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.ReadReq_accesses::total 289629 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 289629 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.demand_accesses::total 289629 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 289629 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 289629 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.488801 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.488801 # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.488801 # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 14052.556668 # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 14052.556668 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 14052.556668 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed system.cpu.dtb_walker_cache.writebacks::writebacks 49457 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 49457 # number of writebacks system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 141571 # number of ReadReq MSHR misses system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 141571 # number of ReadReq MSHR misses system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 141571 # number of demand (read+write) MSHR misses system.cpu.dtb_walker_cache.demand_mshr_misses::total 141571 # number of demand (read+write) MSHR misses system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 141571 # number of overall MSHR misses system.cpu.dtb_walker_cache.overall_mshr_misses::total 141571 # number of overall MSHR misses system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1560743500 # number of ReadReq MSHR miss cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1560743500 # number of ReadReq MSHR miss cycles system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1560743500 # number of demand (read+write) MSHR miss cycles system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1560743500 # number of demand (read+write) MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1560743500 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1560743500 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.488801 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.488801 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.488801 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11024.457693 # average ReadReq mshr miss latency system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11024.457693 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11024.457693 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1662584 # number of replacements system.cpu.dcache.tagsinuse 511.995323 # Cycle average of tags in use system.cpu.dcache.total_refs 19274168 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1663096 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11.589330 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 34335000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.995323 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 11173849 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 11173849 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 8093995 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 8093995 # number of WriteReq hits system.cpu.dcache.demand_hits::cpu.data 19267844 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 19267844 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 19267844 # number of overall hits system.cpu.dcache.overall_hits::total 19267844 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2389581 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2389581 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 320205 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 320205 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 2709786 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2709786 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2709786 # number of overall misses system.cpu.dcache.overall_misses::total 2709786 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 35746262500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 35746262500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 10712131492 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 10712131492 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 46458393992 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 46458393992 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 46458393992 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 46458393992 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 13563430 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13563430 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 8414200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 8414200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 21977630 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 21977630 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 21977630 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 21977630 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.176178 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038055 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.123297 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.123297 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14959.217746 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33453.979457 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 17144.672676 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 17144.672676 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 27702492 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4792 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 5780.987479 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1550496 # number of writebacks system.cpu.dcache.writebacks::total 1550496 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1018010 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1018010 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22803 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 22803 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1040813 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 1040813 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 1040813 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 1040813 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371571 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1371571 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 297402 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 297402 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 1668973 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 1668973 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1668973 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1668973 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18013626000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 18013626000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9484899492 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 9484899492 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27498525492 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 27498525492 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27498525492 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 27498525492 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207760000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207760000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1392508500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1392508500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86600268500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 86600268500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.101123 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035345 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075940 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075940 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13133.571649 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31892.520871 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16476.315370 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16476.315370 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed ---------- End Simulation Statistics ----------