---------- Begin Simulation Statistics ---------- sim_seconds 51.667476 # Number of seconds simulated sim_ticks 51667476471000 # Number of ticks simulated final_tick 51667476471000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 274767 # Simulator instruction rate (inst/s) host_op_rate 322852 # Simulator op (including micro ops) rate (op/s) host_tick_rate 15389929524 # Simulator tick rate (ticks/s) host_mem_usage 683068 # Number of bytes of host memory used host_seconds 3357.23 # Real time elapsed on the host sim_insts 922453344 # Number of instructions simulated sim_ops 1083887959 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 349632 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 295488 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 10205120 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 93689288 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 408000 # Number of bytes read from this memory system.physmem.bytes_read::total 104947528 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 10205120 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 10205120 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 87402048 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::total 87422628 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 5463 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 4617 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 159455 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1463908 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6375 # Number of read requests responded to by this memory system.physmem.num_reads::total 1639818 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1365657 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::total 1368230 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 6767 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 5719 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 197515 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1813313 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 7897 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2031211 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 197515 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 197515 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1691626 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1692024 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1691626 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 6767 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 5719 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 197515 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1813711 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 7897 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3723235 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1639818 # Number of read requests accepted system.physmem.writeReqs 1368230 # Number of write requests accepted system.physmem.readBursts 1639818 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1368230 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 104895040 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 53312 # Total number of bytes read from write queue system.physmem.bytesWritten 87421376 # Total number of bytes written to DRAM system.physmem.bytesReadSys 104947528 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 87422628 # Total written bytes from the system interface side system.physmem.servicedByWrQ 833 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2255 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 99403 # Per bank write bursts system.physmem.perBankRdBursts::1 105228 # Per bank write bursts system.physmem.perBankRdBursts::2 100047 # Per bank write bursts system.physmem.perBankRdBursts::3 95494 # Per bank write bursts system.physmem.perBankRdBursts::4 102929 # Per bank write bursts system.physmem.perBankRdBursts::5 111535 # Per bank write bursts system.physmem.perBankRdBursts::6 97078 # Per bank write bursts system.physmem.perBankRdBursts::7 98055 # Per bank write bursts system.physmem.perBankRdBursts::8 92724 # Per bank write bursts system.physmem.perBankRdBursts::9 154002 # Per bank write bursts system.physmem.perBankRdBursts::10 99475 # Per bank write bursts system.physmem.perBankRdBursts::11 105000 # Per bank write bursts system.physmem.perBankRdBursts::12 94287 # Per bank write bursts system.physmem.perBankRdBursts::13 95690 # Per bank write bursts system.physmem.perBankRdBursts::14 90913 # Per bank write bursts system.physmem.perBankRdBursts::15 97125 # Per bank write bursts system.physmem.perBankWrBursts::0 83951 # Per bank write bursts system.physmem.perBankWrBursts::1 87043 # Per bank write bursts system.physmem.perBankWrBursts::2 85245 # Per bank write bursts system.physmem.perBankWrBursts::3 83208 # Per bank write bursts system.physmem.perBankWrBursts::4 88814 # Per bank write bursts system.physmem.perBankWrBursts::5 93904 # Per bank write bursts system.physmem.perBankWrBursts::6 83820 # Per bank write bursts system.physmem.perBankWrBursts::7 85248 # Per bank write bursts system.physmem.perBankWrBursts::8 81467 # Per bank write bursts system.physmem.perBankWrBursts::9 88240 # Per bank write bursts system.physmem.perBankWrBursts::10 85354 # Per bank write bursts system.physmem.perBankWrBursts::11 89463 # Per bank write bursts system.physmem.perBankWrBursts::12 82403 # Per bank write bursts system.physmem.perBankWrBursts::13 83577 # Per bank write bursts system.physmem.perBankWrBursts::14 80367 # Per bank write bursts system.physmem.perBankWrBursts::15 83855 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 37 # Number of times write queue was full causing retry system.physmem.totGap 51667474307000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 1639803 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1365657 # Write request sizes (log2) system.physmem.rdQLenPdf::0 1314237 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 318417 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 918 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 337 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 465 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 530 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 537 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1148 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 676 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 338 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 362 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 180 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 165 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 121 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 112 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 95 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 53 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 14698 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 18189 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 67736 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 80790 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 82454 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 81257 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 81296 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 82033 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 83039 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 82637 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 83634 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 86681 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 83517 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 83880 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 94578 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 83323 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 84131 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 81331 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 2502 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 677 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 616 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 411 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 474 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 481 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 385 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 283 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 418 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 298 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 289 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 267 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 296 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 241 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 222 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 230 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 242 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 145 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 147 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 151 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 174 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 153 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 129 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 160 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 206 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 109 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 646147 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 297.635603 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 173.901229 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 324.036577 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 253673 39.26% 39.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 155474 24.06% 63.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 60360 9.34% 72.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 34960 5.41% 78.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 25496 3.95% 82.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 18768 2.90% 84.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 14047 2.17% 87.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 13088 2.03% 89.12% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 70281 10.88% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 646147 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 79019 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 20.741467 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 283.796699 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-4095 79016 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 79019 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 79019 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 17.286463 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 16.794878 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 6.949851 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16-19 76956 97.39% 97.39% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20-23 330 0.42% 97.81% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-27 47 0.06% 97.87% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 101 0.13% 97.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 35 0.04% 98.04% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 85 0.11% 98.15% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 245 0.31% 98.46% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 21 0.03% 98.48% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 324 0.41% 98.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 69 0.09% 98.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 26 0.03% 99.01% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 53 0.07% 99.08% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 312 0.39% 99.47% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 39 0.05% 99.52% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 28 0.04% 99.56% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 118 0.15% 99.71% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-83 171 0.22% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 2 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::120-123 2 0.00% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::124-127 3 0.00% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 3 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 6 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 79019 # Writes before turning the bus around for reads system.physmem.totQLat 26490910104 # Total ticks spent queuing system.physmem.totMemAccLat 57221878854 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 8194925000 # Total ticks spent in databus transfers system.physmem.avgQLat 16163.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 34913.00 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.03 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.69 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.03 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.69 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 25.57 # Average write queue length when enqueuing system.physmem.readRowHits 1332864 # Number of row buffer hits during reads system.physmem.writeRowHits 1025932 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.32 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes system.physmem.avgGap 17176412.85 # Average gap between requests system.physmem.pageHitRate 78.50 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 2496243960 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 1362037875 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 6316198200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 4479189840 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3374668374480 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 1323055672425 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 29839910639250 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 34552288356030 # Total energy per rank (pJ) system.physmem_0.averagePower 668.743489 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 49640417958020 # Time in different power states system.physmem_0.memoryStateTime::REF 1725290580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 301767793230 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 2388627360 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 1303318500 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 6467877000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 4372224480 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3374668374480 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 1316624734350 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 29845551821250 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 34551376977420 # Total energy per rank (pJ) system.physmem_1.averagePower 668.725849 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 49649780004526 # Time in different power states system.physmem_1.memoryStateTime::REF 1725290580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 292405760474 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu.branchPred.lookups 252598760 # Number of BP lookups system.cpu.branchPred.condPredicted 176508431 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 11957032 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 185598793 # Number of BTB lookups system.cpu.branchPred.BTBHits 131565493 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 70.887041 # BTB Hit Percentage system.cpu.branchPred.usedRAS 30959293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2131771 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.walker.walks 560635 # Table walker walks requested system.cpu.dtb.walker.walksLong 560635 # Table walker walks initiated with long descriptors system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20884 # Level at which table walker walks with long descriptors terminate system.cpu.dtb.walker.walksLongTerminationLevel::Level3 178593 # Level at which table walker walks with long descriptors terminate system.cpu.dtb.walker.walkWaitTime::samples 560635 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::0 560635 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::total 560635 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkCompletionTime::samples 199477 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::mean 26985.070961 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::gmean 22842.355807 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::stdev 20873.513445 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::0-65535 197251 98.88% 98.88% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.89% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::131072-196607 1888 0.95% 99.83% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::196608-262143 57 0.03% 99.86% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::262144-327679 109 0.05% 99.92% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::327680-393215 46 0.02% 99.94% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::393216-458751 97 0.05% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::589824-655359 5 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::total 199477 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution system.cpu.dtb.walker.walkPageSizes::4K 178594 89.53% 89.53% # Table walker page sizes translated system.cpu.dtb.walker.walkPageSizes::2M 20884 10.47% 100.00% # Table walker page sizes translated system.cpu.dtb.walker.walkPageSizes::total 199478 # Table walker page sizes translated system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 560635 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 560635 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 199478 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 199478 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 760113 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 178339564 # DTB read hits system.cpu.dtb.read_misses 462901 # DTB read misses system.cpu.dtb.write_hits 158016400 # DTB write hits system.cpu.dtb.write_misses 97734 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 45299 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 78401 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 1394 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 14946 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 23063 # Number of TLB faults due to permissions restrictions system.cpu.dtb.read_accesses 178802465 # DTB read accesses system.cpu.dtb.write_accesses 158114134 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.hits 336355964 # DTB hits system.cpu.dtb.misses 560635 # DTB misses system.cpu.dtb.accesses 336916599 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.walker.walks 134932 # Table walker walks requested system.cpu.itb.walker.walksLong 134932 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1079 # Level at which table walker walks with long descriptors terminate system.cpu.itb.walker.walksLongTerminationLevel::Level3 117658 # Level at which table walker walks with long descriptors terminate system.cpu.itb.walker.walkWaitTime::samples 134932 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::0 134932 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::total 134932 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkCompletionTime::samples 118737 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::mean 30245.892182 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::gmean 25862.614601 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::stdev 23195.505917 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::0-32767 58684 49.42% 49.42% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::32768-65535 57510 48.43% 97.86% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::65536-98303 2 0.00% 97.86% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::98304-131071 7 0.01% 97.87% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-163839 1905 1.60% 99.47% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::163840-196607 424 0.36% 99.83% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::196608-229375 23 0.02% 99.85% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::229376-262143 17 0.01% 99.86% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::262144-294911 94 0.08% 99.94% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::294912-327679 21 0.02% 99.96% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::327680-360447 17 0.01% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::360448-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::393216-425983 17 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::425984-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::total 118737 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution system.cpu.itb.walker.walkPageSizes::4K 117658 99.09% 99.09% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::2M 1079 0.91% 100.00% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::total 118737 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134932 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 134932 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118737 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 118737 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 253669 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 439091546 # ITB inst hits system.cpu.itb.inst_misses 134932 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 45299 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID system.cpu.itb.flush_entries 56478 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 354973 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.inst_accesses 439226478 # ITB inst accesses system.cpu.itb.hits 439091546 # DTB hits system.cpu.itb.misses 134932 # DTB misses system.cpu.itb.accesses 439226478 # DTB accesses system.cpu.numCycles 2564620605 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 922453344 # Number of instructions committed system.cpu.committedOps 1083887959 # Number of ops (including micro ops) committed system.cpu.discardedOps 92875630 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 7622 # Number of times Execute suspended instruction fetching system.cpu.quiesceCycles 100771468164 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.cpi 2.780217 # CPI: cycles per instruction system.cpu.ipc 0.359684 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16482 # number of quiesce instructions executed system.cpu.tickCycles 1741581813 # Number of cycles that the object actually ticked system.cpu.idleCycles 823038792 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 10731841 # number of replacements system.cpu.dcache.tags.tagsinuse 511.930081 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 320513038 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 10732353 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 29.864191 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.930081 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 393 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1346389769 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1346389769 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 164045150 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 164045150 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 147553918 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 147553918 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 512343 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 512343 # number of SoftPFReq hits system.cpu.dcache.WriteLineReq_hits::cpu.data 335860 # number of WriteLineReq hits system.cpu.dcache.WriteLineReq_hits::total 335860 # number of WriteLineReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3854660 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3854660 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 4163151 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 4163151 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 311599068 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 311599068 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 312111411 # number of overall hits system.cpu.dcache.overall_hits::total 312111411 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 6370722 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 6370722 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 4130704 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 4130704 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1398816 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1398816 # number of SoftPFReq misses system.cpu.dcache.WriteLineReq_misses::cpu.data 1238819 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_misses::total 1238819 # number of WriteLineReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 310200 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 310200 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses system.cpu.dcache.demand_misses::cpu.data 10501426 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 10501426 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 11900242 # number of overall misses system.cpu.dcache.overall_misses::total 11900242 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 117402431000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 117402431000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 199951337000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 199951337000 # number of WriteReq miss cycles system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 84556806000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_miss_latency::total 84556806000 # number of WriteLineReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5139718000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 5139718000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 317353768000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 317353768000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 317353768000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 317353768000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 170415872 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 170415872 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 151684622 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 151684622 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 1911159 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 1911159 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::cpu.data 1574679 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 1574679 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4164860 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 4164860 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 4163152 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 4163152 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 322100494 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 322100494 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 324011653 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 324011653 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037383 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.037383 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027232 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.027232 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.731920 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.731920 # miss rate for SoftPFReq accesses system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786712 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_miss_rate::total 0.786712 # miss rate for WriteLineReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074480 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074480 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.032603 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.032603 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.036728 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036728 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18428.434171 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 18428.434171 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48406.116003 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 48406.116003 # average WriteReq miss latency system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 68255.980898 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_avg_miss_latency::total 68255.980898 # average WriteLineReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16569.045777 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16569.045777 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 30220.064208 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 30220.064208 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 26667.841545 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 26667.841545 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 8243774 # number of writebacks system.cpu.dcache.writebacks::total 8243774 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 770626 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 770626 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1821654 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1821654 # number of WriteReq MSHR hits system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 153 # number of WriteLineReq MSHR hits system.cpu.dcache.WriteLineReq_mshr_hits::total 153 # number of WriteLineReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 68982 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 68982 # number of LoadLockedReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 2592280 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 2592280 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 2592280 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 2592280 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5600096 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 5600096 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2309050 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2309050 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1391260 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1391260 # number of SoftPFReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1238666 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_misses::total 1238666 # number of WriteLineReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241218 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 241218 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 7909146 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 7909146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9300406 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9300406 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 96067975500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 96067975500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106000226500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 106000226500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26589323500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26589323500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 83310681500 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 83310681500 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3491728500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3491728500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 202068202000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 202068202000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 228657525500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 228657525500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197287500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197287500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207449000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207449000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12404736500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 12404736500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032861 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032861 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015223 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015223 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.727967 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.727967 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786615 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786615 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057917 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057917 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024555 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.024555 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028704 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.028704 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17154.701544 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17154.701544 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45906.423204 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45906.423204 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19111.685451 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19111.685451 # average SoftPFReq mshr miss latency system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 67258.390478 # average WriteLineReq mshr miss latency system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 67258.390478 # average WriteLineReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14475.406064 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14475.406064 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25548.675167 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 25548.675167 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24585.757385 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 24585.757385 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183912.143514 # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183912.143514 # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184164.510770 # average WriteReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184164.510770 # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184038.343991 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184038.343991 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 24176986 # number of replacements system.cpu.icache.tags.tagsinuse 511.872408 # Cycle average of tags in use system.cpu.icache.tags.total_refs 414546703 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 24177498 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 17.145972 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 39504620500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.872408 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999751 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999751 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 462901718 # Number of tag accesses system.cpu.icache.tags.data_accesses 462901718 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 414546703 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 414546703 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 414546703 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 414546703 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 414546703 # number of overall hits system.cpu.icache.overall_hits::total 414546703 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 24177508 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 24177508 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 24177508 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 24177508 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 24177508 # number of overall misses system.cpu.icache.overall_misses::total 24177508 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 327600086000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 327600086000 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 327600086000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 327600086000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 327600086000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 327600086000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 438724211 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 438724211 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 438724211 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 438724211 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 438724211 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 438724211 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055109 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.055109 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.055109 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.055109 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.055109 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.055109 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13549.787100 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 13549.787100 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 13549.787100 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 13549.787100 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 13549.787100 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 13549.787100 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 24176986 # number of writebacks system.cpu.icache.writebacks::total 24176986 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24177508 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 24177508 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 24177508 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 24177508 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 24177508 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 24177508 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303422579000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 303422579000 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303422579000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 303422579000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303422579000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 303422579000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6746864000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6746864000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6746864000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 6746864000 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.055109 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.055109 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.055109 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.055109 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.055109 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.055109 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12549.787141 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12549.787141 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12549.787141 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 12549.787141 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12549.787141 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 12549.787141 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1490234 # number of replacements system.cpu.l2cache.tags.tagsinuse 65213.875092 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 65897094 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1553867 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 42.408452 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 36600562500 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 37061.912307 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 323.258711 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 399.460797 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 7867.228358 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 19562.014919 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.565520 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004933 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006095 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.120044 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.298493 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.995085 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 237 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 63396 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 236 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 513 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5534 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54861 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003616 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.967346 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 573646968 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 573646968 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 914477 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 280144 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1194621 # number of ReadReq hits system.cpu.l2cache.WritebackDirty_hits::writebacks 8243774 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 8243774 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 24173277 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 24173277 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 10400 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 10400 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 1641430 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1641430 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24070330 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 24070330 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6918127 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 6918127 # number of ReadSharedReq hits system.cpu.l2cache.InvalidateReq_hits::cpu.data 707471 # number of InvalidateReq hits system.cpu.l2cache.InvalidateReq_hits::total 707471 # number of InvalidateReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 914477 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 280144 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 24070330 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 8559557 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 33824508 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 914477 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 280144 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 24070330 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 8559557 # number of overall hits system.cpu.l2cache.overall_hits::total 33824508 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5463 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4617 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 10080 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 37497 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 37497 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 619977 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 619977 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107175 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 107175 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 314193 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 314193 # number of ReadSharedReq misses system.cpu.l2cache.InvalidateReq_misses::cpu.data 531195 # number of InvalidateReq misses system.cpu.l2cache.InvalidateReq_misses::total 531195 # number of InvalidateReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 5463 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 4617 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 107175 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 934170 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 1051425 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 5463 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 4617 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 107175 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 934170 # number of overall misses system.cpu.l2cache.overall_misses::total 1051425 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 750857500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 630554000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 1381411500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1438781000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 1438781000 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 82239355500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 82239355500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14186388500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 14186388500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 42349642500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 42349642500 # number of ReadSharedReq miss cycles system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 73756780500 # number of InvalidateReq miss cycles system.cpu.l2cache.InvalidateReq_miss_latency::total 73756780500 # number of InvalidateReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 750857500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 630554000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 14186388500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 124588998000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 140156798000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 750857500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 630554000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 14186388500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 124588998000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 140156798000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 919940 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 284761 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1204701 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::writebacks 8243774 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 8243774 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 24173277 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 24173277 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 47897 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 47897 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2261407 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2261407 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24177505 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 24177505 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7232320 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 7232320 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1238666 # number of InvalidateReq accesses(hits+misses) system.cpu.l2cache.InvalidateReq_accesses::total 1238666 # number of InvalidateReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 919940 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 284761 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 24177505 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 9493727 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 34875933 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 919940 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 284761 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 24177505 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9493727 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 34875933 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.005938 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.016214 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.008367 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782867 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782867 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.274155 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.274155 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004433 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004433 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043443 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043443 # miss rate for ReadSharedReq accesses system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.428844 # miss rate for InvalidateReq accesses system.cpu.l2cache.InvalidateReq_miss_rate::total 0.428844 # miss rate for InvalidateReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.005938 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.016214 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004433 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.098399 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.030148 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.005938 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.016214 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004433 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.098399 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.030148 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137444.169870 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136572.233052 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 137044.791667 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38370.562978 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38370.562978 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132649.042626 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132649.042626 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132366.582692 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132366.582692 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134788.625144 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134788.625144 # average ReadSharedReq miss latency system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 138850.667834 # average InvalidateReq miss latency system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 138850.667834 # average InvalidateReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137444.169870 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136572.233052 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132366.582692 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133368.656668 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 133301.755237 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137444.169870 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136572.233052 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132366.582692 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133368.656668 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 133301.755237 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1259026 # number of writebacks system.cpu.l2cache.writebacks::total 1259026 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5463 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4617 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 10080 # number of ReadReq MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 3 # number of CleanEvict MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37497 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 37497 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 619977 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 619977 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 107172 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 107172 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 314172 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 314172 # number of ReadSharedReq MSHR misses system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 531195 # number of InvalidateReq MSHR misses system.cpu.l2cache.InvalidateReq_mshr_misses::total 531195 # number of InvalidateReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5463 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4617 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 107172 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 934149 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 1051401 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5463 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4617 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 107172 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 934149 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1051401 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 86006 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119712 # number of overall MSHR uncacheable misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 696227500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 584384000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1280611500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2550264500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2550264500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 69500 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 69500 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 76039573524 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 76039573524 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13114406000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13114406000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 39205480000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 39205480000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 68444830500 # number of InvalidateReq MSHR miss cycles system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 68444830500 # number of InvalidateReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 696227500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 584384000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13114406000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115245053524 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 129640071024 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 696227500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 584384000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13114406000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115245053524 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 129640071024 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5936074000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5776017500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11712091500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5819225500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5819225500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5936074000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11595243000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 17531317000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.005938 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.016214 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008367 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782867 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782867 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.274155 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.274155 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004433 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004433 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043440 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043440 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.428844 # mshr miss rate for InvalidateReq accesses system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.428844 # mshr miss rate for InvalidateReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.005938 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.016214 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004433 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.098396 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.030147 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.005938 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.016214 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004433 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.098396 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.030147 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127444.169870 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126572.233052 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127044.791667 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.494333 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.494333 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122649.023309 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122649.023309 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122367.838615 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122367.838615 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124789.860331 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124789.860331 # average ReadSharedReq mshr miss latency system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128850.667834 # average InvalidateReq mshr miss latency system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128850.667834 # average InvalidateReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127444.169870 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126572.233052 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122367.838615 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123369.027344 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123302.213926 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127444.169870 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126572.233052 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122367.838615 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123369.027344 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123302.213926 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171410.437131 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136177.609702 # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172646.576277 # average WriteReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172646.576277 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172028.589232 # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146445.778201 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 70561172 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 35651281 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4392 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 2272 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2272 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 1729330 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 33139930 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 9609467 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 24176986 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2728127 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 47900 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 47901 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2261407 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2261407 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 24177508 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 7241194 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 1345330 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateResp 1238666 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72636616 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32428005 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 687897 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2160128 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 107912646 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3098035136 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1135439954 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2278088 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7359520 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 4243112698 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 2160696 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 38442129 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.018241 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.133822 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 37740909 98.18% 98.18% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 701220 1.82% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 38442129 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 68252447493 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1464392 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 36351871671 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 14935181922 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 403175920 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 1240232910 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 40322 # Transaction distribution system.iobus.trans_dist::ReadResp 40322 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 353786 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7492360 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 42165000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 332500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 25683500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 34144500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 567247076 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 147762000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 115483 # number of replacements system.iocache.tags.tagsinuse 10.440004 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13160148727000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.520843 # Average occupied blocks per requestor system.iocache.tags.occ_blocks::realview.ide 6.919161 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.220053 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.432448 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.652500 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1039866 # Number of tag accesses system.iocache.tags.data_accesses 1039866 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses system.iocache.demand_misses::total 8877 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses system.iocache.overall_misses::realview.ide 8837 # number of overall misses system.iocache.overall_misses::total 8877 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::realview.ide 1647976559 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 1653046059 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles system.iocache.WriteLineReq_miss_latency::realview.ide 13408898017 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 13408898017 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::realview.ide 1647976559 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 1653397059 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles system.iocache.overall_miss_latency::realview.ide 1647976559 # number of overall miss cycles system.iocache.overall_miss_latency::total 1653397059 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::realview.ide 186485.974765 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 186279.700135 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125711.561698 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 125711.561698 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency system.iocache.demand_avg_miss_latency::realview.ide 186485.974765 # average overall miss latency system.iocache.demand_avg_miss_latency::total 186256.286921 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 186485.974765 # average overall miss latency system.iocache.overall_avg_miss_latency::total 186256.286921 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 33362 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 3432 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 9.720862 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::realview.ide 1206126559 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 1209346059 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8070540171 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 8070540171 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 1206126559 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 1209547059 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 1206126559 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 1209547059 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136485.974765 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 136279.700135 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75663.205683 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75663.205683 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 136485.974765 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 136256.286921 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 136485.974765 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 136256.286921 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 86006 # Transaction distribution system.membus.trans_dist::ReadResp 526304 # Transaction distribution system.membus.trans_dist::WriteReq 33706 # Transaction distribution system.membus.trans_dist::WriteResp 33706 # Transaction distribution system.membus.trans_dist::WritebackDirty 1365657 # Transaction distribution system.membus.trans_dist::CleanEvict 238956 # Transaction distribution system.membus.trans_dist::UpgradeReq 38308 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 7 # Transaction distribution system.membus.trans_dist::ReadExReq 1150364 # Transaction distribution system.membus.trans_dist::ReadExResp 1150364 # Transaction distribution system.membus.trans_dist::ReadSharedReq 440298 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4800126 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4929778 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237399 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 237399 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 5167177 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 185137772 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 185308178 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7232384 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7232384 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 192540562 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 3164 # Total snoops (count) system.membus.snoop_fanout::samples 3459998 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 3459998 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 3459998 # Request fanout histogram system.membus.reqLayer0.occupancy 102421000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 5498500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 9252697708 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 8691723530 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 44915426 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks ---------- End Simulation Statistics ----------